CENG 342 Digital Systems Regular Sequential Circuit Larry Pyeatt - PowerPoint PPT Presentation

CENG 342 – Digital Systems Regular Sequential Circuit Larry Pyeatt SDSM&T

Mealy vs Moore Moore machine is a finite-state machine whose output values are determined solely by its current state. Mealy machine is a finite-state machine whose output values are determined both by its current state and the current inputs. Combinational Combinational Inputs Inputs Logic Circuit Logic Circuit (Next State) (Next State) Memory Memory Devices Devices (Flip−Flops) (Flip−Flops) Combinational Combinational Logic Circuit Logic Circuit Outputs Outputs (Output Logic) (Output Logic)

Basic Memory Elements Latch and Flip Flop: 1-bit storage element. Comes in J-K, D, and S-R varieties. We focus on D. Characteristics of D Latch and D Flip Flop (FF): c q* c q* c q* d q d q d q 0 q 0 q 0 q 1 q 1 q clk clk clk 1 d d d D Latch Positive edge Negative edge triggered D FF triggered D FF D latch depends on the level of the clock, so it is level sensitive . D FF depends on the rising (changes from 0 to 1) or falling (changes from 1 to 0) edge of the clock, so it is edge triggered . A small triangle is used to show that the storage device is edge-triggered. Note: q* represents the next value of q.

Finite State Machine Design Methodology Two main types: synchronous and asynchronous. Synchronous: uses a global clock to drive all latches/flip-flops in the circuit. Asynchronous: does not use a global clock signal. The combinational logic blocks of each layer drive the clocks of the following layers (and possibly their own clocks). Very tricky, but can give very high performance. Synchronous Design Methodology assumes that all storage elements are controlled by a global clock signal and the data is sampled at the rising or falling edge of the clock signal. Our design will follow this synchronous design methodology. The storage components can be separated from the combinational logic circuit(s) and this will significantly simplify the development process.

Synchronous System Block diagram of a 2-state synchronous system: State register: a D FF (register) Next-state logic: combinational logic to determine the new value of the register Output logic: combinational logic to generate the output o u t p u t o u t p u t lo g ic d q n e x t -st a t e st a t e _re g e x t e rn a l lo g ic st a t e _n e x t clk in p u t clk Mealy or Moore?

Timing Constraints for Flip-Flops – Part 1 Flip-flops have timing constraints. The most important ones are: T setup : the time interval in which the d signal must be stable before the clock edge T hold : the time interval in which the d signal must be stable after the clock edge. T cq : clock-to-q delay, the propagation delay required for the d input to show up at the q output after the sampling edge of clock. If the d signal changes within the setup or hold time window, the value stored may not be the one intended. These situations are known as setup time violations or hold time violations . clk d q setup time T hold T cq violation T setup

Timing Constraints for Flip-Flops – Part 2 T clock is the minimal time clock (period between two sampling edges). The next value must be generated and stabilized during this period. f max is the maximal clock frequency for a sequential circuit using the flip-flop. It is the reciprocal of T clock. 1 f max = T clock The Nexys A7 board provides a 100MHz system clock (10ns period). Timing information can be found from the View Design Summary after synthesis. Coding strategy: separate the memory component (D flip-flop) from the combinational logic. View as two pieces: register and combinational circuit Regular sequential circuit (Chapter 4): the state transition follows regular pattern like counter or shift register FSM (Chapter 5): does not follow simple regular pattern FSMD (Chapter 6): FSM + regular sequential circuit

D Flip Flop We focus on positive edge triggered FF because that is what the Xilinx chip has. The value of D is transferred to Q at the rising edge (from 0 to 1) of clock signals. There are variants: D FF without reset D FF with asynchronous reset: reset signal (independent of clk) to clear FF to ‘0’. D FF with enable: maintain synchronism between a fast subsystem and a slow subsystem. Not shown is a D FF with synchronous reset: reset signal is synchronized with clock to clear FF to ‘0’. In FPGA design, this is preferred to asynchronous reset. Nexys A7 board has a dedicated button for use as a system reset. It is labeled “CPU Reset” on the board and appears as “reset” in the master xdc file. rst clk en q* rst clk q* c q* en 1 - - 0 d q d q 1 - 0 d q 0 q 0 0 - q 0 0 q clk 1 q clk 0 1 - q clk 0 1 q rst d rst 0 0 q 0 d 0 1 d D FF D FF with asynchronous D FF with enable reset

Representing Clock Edges in VHDL Within a process, a clock change is represented using: CLK’event Which is ‘true’ if the clock is changing at the current time. For a positive edge: 1 CLK’event and CLK=’1’ or 1 rising_edge(CLK) Which is ‘true’ if the clock is changing to ‘1’. For a negative edge: 1 CLK’event and CLK=‘0’ or 1 falling_edge (CLK) rising_edge and falling_edge are functions defined in the std_logic_1164 Package

VHDL code for D flip-flop - Part 1 D FF without reset signal: at rising edges of clock signal, the value of D is transferred to Q, otherwise Q is unchanged. 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity d_ff is 5 port( 6 clk: in std_logic; 7 d: in std_logic; 8 q: out std_logic 9 ); c q* d q 10 end d_ff; 0 q 11 1 q 12 architecture arch of d_ff is clk d 13 begin 14 process(clk) begin 15 if (clk’event and clk=’1’) then 16 q <= d; 17 end if; 18 end process; 19 20 end arch;

VHDL code for D flip-flop - Part 2 D FF with asynchronous reset signal: Reset signal can clear the FF at any time. 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity d_ff_reset is 5 port( 6 clk, rst: in std_logic; 7 d: in std_logic; 8 q: out std_logic 9 ); rst clk q* 10 end d_ff_reset; d q 1 - 0 11 0 0 q 12 architecture arch of d_ff_reset is clk 13 begin 0 1 q rst process(clk,rst) 14 0 d begin 15 if (rst=’1’) then 16 q <=’0’; 17 elsif (clk’event and clk=’1’) then 18 q <= d; 19 end if; 20 end process; 21 22 end arch;

VHDL code for D flip-flop - Part 2 D FF with enable signal: If en is zero, clock is ignored. 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity d_ff_en is port( 5 clk, reset: in std_logic; 6 en: in std_logic; 7 d: in std_logic; 8 q: out std_logic 9 10 ); rst clk en q* 11 end d_ff_en; 1 - - 0 en 12 d q 0 0 - q 13 architecture arch of d_ff_en is 0 1 - q 14 begin clk process(clk,reset) 0 0 q 15 rst begin 16 0 1 d 17 if (reset=’1’) then 18 q <=’0’; 19 elsif (clk’event and clk=’1’) then 20 if (en=’1’) then 21 q <= d; 22 end if; 23 end if; 24 end process; 25 end arch;

D FF with enable signal – 2 nd approach The enable signal is synchronous, the circuit can be built with a D FF and simple next-state logic rst clk en q* d 1 r_n e x t en 1 - - 0 d q q d q 0 0 0 - q r_re g clk clk 0 1 - q e n rst 0 0 q re se t clk 0 1 d re se t Coding development: separate memory from combinational circuits: 1 Use an individual VHDL code segment to infer memory elements. The segment should be a standard description of D FF or register 2 Use the suffix _reg to represent the output of a D FF or a register. 3 Use the suffix _next to indicate the next value (the d input) of a D FF or a register.

VHDL 1 architecture two_seg_arch of d_ff_en is signal r_reg, r_next: std_logic; 2 3 begin -- D FF 4 process(clk,reset) 5 begin 6 if (reset=’1’) then 7 r_reg <=’0’; 8 elsif (clk’event and clk=’1’) then 9 r_reg <= r_next; 10 end if; 11 end process; 12 -- next-state logic 13 r_next <= d when en =’1’ else r_reg; 14 -- output logic 15 q <= r_reg; 16 17 end two_seg_arch;