CENG 342 Digital Systems Shift Registers Larry Pyeatt SDSM&T - PowerPoint PPT Presentation

CENG 342 – Digital Systems Shift Registers Larry Pyeatt SDSM&T

Compare Two Circuits What is the difference between these two circuits? What are their functions? d q d q d q d q I 3 I 2 I 1 I 0 clk clk clk clk R Q 3 Q 2 Q 1 Q 0 rst rst rst rst In Out d q d q d q d q In Out clk clk clk clk R Q 3 Q 2 Q 1 Q 0 rst rst rst rst

Basic Shift Register Free-running shift register: the simplest shift register that shift 1 bit to right or left in each clock cycle. No control signal is required. N-bit free-running shift-right register: serial mode (one input and one output, the register is shifted in the same direction) Example: 4-bit shift-right register In In Out Q 1 Q 2 Q 3 Q 4 Q 1 Q 2 Q 3 Q 4 Out d q d q d q d q t 0 1 U U U U clk clk clk clk t 1 0 1 U U U t 2 1 0 1 U U t 3 1 1 0 1 U t 4 1 1 1 0 1 t 5 0 1 1 1 0 t 6 0 0 1 1 1 t 7 0 0 0 1 1

Implementation It can be implemented as a sequential circuit with a 4-bit D register. 4 Output d q q Logic 1-bit right 4 4 1 shifter d clk 1 rst clk reset

VHDL Implementation 13 architecture arch of free_run_shift_reg is 14 signal r_reg: std_logic_vector(N-1 downto 0); 15 signal r_next: std_logic_vector(N-1 downto 0); 16 begin -- register 17 1 library ieee; process(clk,reset) 18 2 use ieee.std_logic_1164.all; begin 19 3 if (reset=’1’) then 20 4 entity free_run_shift_reg is r_reg <= (others=>’0’); 21 generic(N: integer := 4); 5 elsif (clk’event and clk=’1’) then 22 port( 6 r_reg <= r_next; 23 clk, reset: in std_logic; 7 end if; 24 s_in: in std_logic;-- one bit 8 end process; 25 s_out: out std_logic--one bit 9 26 ); 10 -- next-state logic 27 11 end free_run_shift_reg; r_next <= s_in & r_reg(N-1 downto 1); 28 29 -- output 30 s_out <= r_reg(0); 31 32 end arch;

Universal Shift Register A register capable of shifting in one direction is a unidirectional shift register. A bidirectional shift register is able to shift in both directions. A universal shift register can load parallel data, shift left, shift right, or simply retain its contents. A 2-bit control signal is used to determine the specific operation at each clock cycle. Function Table for universal shift register: Control Operation 0 0 No change 0 1 Shift Left 1 0 Shift Right 1 1 Parallel load

Universal Shift Register – Block diagram 4 00 4 01 d q q 1-bit left 10 4 4 4 shifter 4 11 clk 1 rst 1-bit right 4 d 0 shifter 4 1 d 3 d 4 control 2 clk reset

VHDL Implementation – Part 1 1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity univ_shift_reg is generic(N: integer := 4); 5 port( 6 clk, reset: in std_logic; 7 ctrl: in std_logic_vector(1 downto 0); 8 d: in std_logic_vector(N-1 downto 0); 9 q: out std_logic_vector(N-1 downto 0) 10 ); 11 12 end univ_shift_reg;

VHDL Implementation – Part 2 14 architecture arch of univ_shift_reg is signal r_reg: std_logic_vector(N-1 downto 0); 15 signal r_next: std_logic_vector(N-1 downto 0); 16 17 begin -- register 18 process(clk,reset) 19 begin 20 if (reset=’1’) then 21 r_reg <= (others=>’0’); 22 elsif (clk’event and clk=’1’) then 23 r_reg <= r_next; 24 end if; 25 end process; 26 -- next-state logic 27 with ctrl select 28 r_next <= r_reg when "00", --no op 29 r_reg(N-2 downto 0) & d(0) when "01", --shift left and insert d(0) 30 d(N-1) & r_reg(N-1 downto 1) when "10",--shift right and insert d(N-1) 31 d when others; -- load 32 -- output 33 q <= r_reg; 34 35 end arch;