SLIDE 1
CENG 342 – Digital Systems
Shift Registers Larry Pyeatt
SDSM&T
CENG 342 Digital Systems Shift Registers Larry Pyeatt SDSM&T - - PowerPoint PPT Presentation
CENG 342 Digital Systems Shift Registers Larry Pyeatt SDSM&T - - PowerPoint PPT Presentation
CENG 342 Digital Systems Shift Registers Larry Pyeatt SDSM&T Compare Two Circuits What is the difference between these two circuits? What are their functions? d q d q d q d q I 3 I 2 I 1 I 0 clk clk clk clk R Q 3 Q 2 Q 1 Q
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SLIDE 3
Basic Shift Register
Free-running shift register: the simplest shift register that shift 1 bit to right or left in each clock cycle. No control signal is required. N-bit free-running shift-right register: serial mode (one input and one output, the register is shifted in the same direction) Example: 4-bit shift-right register
d q clk d q clk d q clk d q clk In Out Q4 Q1 Q2 Q3
In Out Q1 Q2 Q3 Q4 t0 1 U U U U t1 1 U U U t2 1 1 U U t3 1 1 1 U t4 1 1 1 1 t5 1 1 1 t6 1 1 1 t7 1 1
SLIDE 4
Implementation
It can be implemented as a sequential circuit with a 4-bit D register.
d q rst clk 1-bit right shifter Output Logic reset clk d q
1 4 4 4 1
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VHDL Implementation
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity free_run_shift_reg is 5
generic(N: integer := 4);
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port(
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clk, reset: in std_logic;
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s_in: in std_logic;-- one bit
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s_out: out std_logic--one bit
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);
11 end free_run_shift_reg; 13 architecture arch of free_run_shift_reg is 14
signal r_reg: std_logic_vector(N-1 downto 0);
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signal r_next: std_logic_vector(N-1 downto 0);
16 begin 17
- - register
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process(clk,reset)
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begin
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if (reset=’1’) then
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r_reg <= (others=>’0’);
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elsif (clk’event and clk=’1’) then
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r_reg <= r_next;
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end if;
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end process;
26 27
- - next-state logic
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r_next <= s_in & r_reg(N-1 downto 1);
29 30
- - output
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s_out <= r_reg(0);
32 end arch;
SLIDE 6
Universal Shift Register
A register capable of shifting in one direction is a unidirectional shift register. A bidirectional shift register is able to shift in both directions. A universal shift register can load parallel data, shift left, shift right, or simply retain its contents.
A 2-bit control signal is used to determine the specific operation at each clock cycle. Function Table for universal shift register: Control Operation No change 1 Shift Left 1 Shift Right 1 1 Parallel load
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Universal Shift Register – Block diagram
d q rst clk
4 4
11 01 10 00
4 4 4 4 1 4 4 2 4 1
1-bit right shifter shifter 1-bit left q control d reset clk d3 d0
SLIDE 8
VHDL Implementation – Part 1
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity univ_shift_reg is 5
generic(N: integer := 4);
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port(
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clk, reset: in std_logic;
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ctrl: in std_logic_vector(1 downto 0);
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d: in std_logic_vector(N-1 downto 0);
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q: out std_logic_vector(N-1 downto 0)
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);
12 end univ_shift_reg;
SLIDE 9
VHDL Implementation – Part 2
14 architecture arch of univ_shift_reg is 15
signal r_reg: std_logic_vector(N-1 downto 0);
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signal r_next: std_logic_vector(N-1 downto 0);
17 begin 18
- - register
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process(clk,reset)
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begin
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if (reset=’1’) then
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r_reg <= (others=>’0’);
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elsif (clk’event and clk=’1’) then
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r_reg <= r_next;
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end if;
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end process;
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- - next-state logic
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with ctrl select
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r_next <= r_reg when "00", --no op
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r_reg(N-2 downto 0) & d(0) when "01", --shift left and insert d(0)
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d(N-1) & r_reg(N-1 downto 1) when "10",--shift right and insert d(N-1)
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d when others; -- load
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- - output
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q <= r_reg;
35 end arch;