ECED2200 Digital Circuits Serial Protocols, Registers, Shift - - PowerPoint PPT Presentation

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ECED2200 Digital Circuits Serial Protocols, Registers, Shift Registers 23/07/2012 Colin OFlynn - CC BY-SA 1 General Notes See updates to these slides: www.newae.com/teaching These slides licensed under Creative Commons

SLIDE 1

ECED2200 – Digital Circuits

Serial Protocols, Registers, Shift Registers

23/07/2012 Colin O’Flynn - CC BY-SA 1

SLIDE 2

General Notes

See updates to these slides: www.newae.com/teaching
These slides licensed under ‘Creative Commons Attribution-ShareAlike 3.0

Unported License’

These slides are not the complete course – they are extended in-class
You will find the following references useful, see

www.newae.com/teaching for more information/links:

– The book “Bebop to the Boolean Boogie” which is available to Dalhousie Students – Course notes (covers almost everything we will discuss in class) – Various websites such as e.g.: www.play-hookey.com – The book “Contemporary Logic Design”, which was used in previous iterations of the class and you may have already

23/07/2012 Colin O’Flynn - CC BY-SA 2

SLIDE 3

REGISTERS

23/07/2012 Colin O’Flynn - CC BY-SA 3

SLIDE 4

23/07/2012 Colin O’Flynn - CC BY-SA 4

SLIDE 5

Registers

23/07/2012 Colin O’Flynn - CC BY-SA 5

SLIDE 6

SHIFT REGISTERS

23/07/2012 Colin O’Flynn - CC BY-SA 6

SLIDE 7

Serial to Parallel Shift Register

23/07/2012 Colin O’Flynn - CC BY-SA 7

SLIDE 8

Serial to Parallel Shift Register

23/07/2012 Colin O’Flynn - CC BY-SA 8

SLIDE 9

Serial to Parallel Shift Register

23/07/2012 Colin O’Flynn - CC BY-SA 9

SLIDE 10

Serial to Parallel Shift Register

23/07/2012 Colin O’Flynn - CC BY-SA 10

SLIDE 11

SERIAL PROTOCOLS

23/07/2012 Colin O’Flynn - CC BY-SA 11

SLIDE 12

General Characteristics of Serial

Bit Rate
MSB/LSB First
Length of data
Control Lines

23/07/2012 Colin O’Flynn - CC BY-SA 12

SLIDE 13

Serial Peripheral Interface (SPI)

Four lines:

– Data In – Data Out – Clock – Slave Select

23/07/2012 Colin O’Flynn - CC BY-SA 13

SLIDE 14

SPI

23/07/2012 Colin O’Flynn - CC BY-SA 14 Images by Colin M.L. Burnett published under CC BY-SA License

SLIDE 15

SPI

23/07/2012 Colin O’Flynn - CC BY-SA 15 Images by Colin M.L. Burnett published under CC BY-SA License

SLIDE 16

SPI

23/07/2012 Colin O’Flynn - CC BY-SA 16

SCK SS

Images by Colin M.L. Burnett published under CC BY-SA License

SLIDE 17

Inter-IC (I2C)

Two lines:

– Clock – Bidirectional Data

23/07/2012 Colin O’Flynn - CC BY-SA 17

SLIDE 18

I2C

23/07/2012 Colin O’Flynn - CC BY-SA 18 Images by Colin M.L. Burnett published under CC BY-SA License

SLIDE 19

Inter-IC (I2C)

23/07/2012 Colin O’Flynn - CC BY-SA 19 Images by Marcin Florvan released into public domain

SLIDE 20

Asynchronous Serial

Two lines typically:

– Data In – Data Out

23/07/2012 Colin O’Flynn - CC BY-SA 20

SLIDE 21

Asynchronous Serial

23/07/2012 Colin O’Flynn - CC BY-SA 21

SLIDE 22

Universal Serial Bus (USB)

Two Lines

– D+, D- = Both Data Lines

23/07/2012 Colin O’Flynn - CC BY-SA 22

SLIDE 23

Summary

ECED Class Notes
Bebop to the Boolean Boogie

23/07/2012 Colin O’Flynn - CC BY-SA 23