Modelling of the Digital Systems What are the digital systems - - PowerPoint PPT Presentation

Modelling of the Digital Systems

What are the digital systems (circuits)?

• Digital systems are based on binary representation

0 or 1

• Performing function of the Boolean logic

Required circuits Boolean operators (inv, nand, nor, or, and)

• Enabling storing of information in registers

Usually with the clock edge Registers implemented as flip-flops or latches

Boolean Algebra

• Boolean values

Different representations On/OFF – Vdd/Gnd True/False 1/0

• Boolean operators

NOT AND OR

• Examples

A = 1 B = C AND 0 F = /(A+B*C) Z= (/A+B)*(A+/B)

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Truth Tables

• Listing of all possible values of inputs and respective outputs

A not A 1 1 A B A or B 1 1 1 1 1 1 1 A XOR B ?

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Rules of Boolean Algebra

• Commutivity

A + B = B + A A * B = B * A

• Associativity

A+ (B + C) = (A+B)+C A* (B * C) = (A*B)*C

• Distributivity

A*(B+C)=A*B+A*C

• Basic Relationships

A*1=A A+0=A A*0=0 A+1=1 A*A=A A+A=A A*/A=0 A+/A=1

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Rules of Boolean Algebra

• De Morgan’s Law

/(A*B) = /A+/B /(A+B) = /A * /B

• Shannon’s expansion theorem

F(A,B,C,D,…)=(A+F(0,B,C,D,…))*(/A+F(1,B,C,D,…))

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Logic Gates

• Logic Symbols

Equivalent Circuit Representation

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• M. Zwolinski – Digital System Design with VHDL

MINTERM and MAXTERM

• Minterm – Boolean AND function containing one instance of

each variable

• Maxterm – Boolean OR function containing one instance of

each variable A B C Z 1 m0 1 1 m1 1 M2 1 1 M3 1 M4 1 1 1 m5 1 1 M6 1 1 1 1 m7 Z= m0 + m1 + m5 +m7 Z=M2 * M3 * M4 * M6

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Logic Minimization

• Function of a combinational logic circuit can be described by
• ne or more Boolean expressions.

We need optimal implementation of combinational logic! Karnaugh Maps

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• M. Zwolinski – Digital System Design with VHDL

Karnaugh map

• Grouping patterns

Circle the largest possible groups Avoid circles inside circles

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• M. Zwolinski – Digital System Design with VHDL

Number Codes

• Digital representation in set of bits
• Integers

Base 2 – 101 2 hex – 7AF 16 Two’s complement

• 6 = inverting 0110 + 1 = 1010
• Fixed-point numbers

6.25 = 110.01 The point is implicitly stored by knowing the position in advance

• Floating-point numbers

S- sign bit, e –exponent, m – mantisa (-1)s X 1.m X 2e

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Hardware Desciption Languages

• Used to describe digital systems

Different levels of representation: behavioural, structural

• Imperative languages

C, Basic, Assembler

• HDL needs to enable concurrent execution of the statements

Why?

• Example languages

VHDL, Verilog

Concurrent execution

Combinational Code using VHDL

• Combinational logic is stateless

Changes in inputs immediately propagate to outputs In simulator this is however delta cycle delay

• Entities and architectures

Basic structures of VHDL Entity – Symbol (outer view of the block) Architecture - Implementation entity and2 is port (a, b : in BIT; c: out BIT); end entity and2; architecture struc of And2 is begin c <= a and b; end architecture struc;

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Handling more complex examples

A B C Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Use K-map to get result !

entity comb_function is port (a, b, c : in BIT; z: out BIT); end entity comb_function; architecture expression of comb_function is begin z <= (not a and b) or (a and c); end architecture expression; Why parentheses?

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• M. Zwolinski – Digital System Design with VHDL

Hierarchy

architecture netlist2 of comb_function is component And2 is port (x, y : in BIT; z: out BIT); end component And2; component Or2 is port (x, y : in BIT; z: out BIT); end component Or2; component Not1 is port (x : in BIT; z: out BIT); end component Not1; signal p, q, r : BIT; begin g1: Not1 port map (a, p); g2: And2 port map (p, b, q); g3: And2 port map (a, c, r); g4: Or2 port map (q, r, z); end architecture netlist; 15

• M. Zwolinski – Digital System Design with VHDL

Timing

• Timing Diagram

Boolean gates require some time for propagation In reality circuits and wires have intrinsic delay Usually when modeling in VHDL it is not required to handle the timing In some specific cases is however this recommended Sole combinational logic, race conditions, hazards

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• M. Zwolinski – Digital System Design with VHDL

Signal Assignments

Z <= x and y; Several ways of modelling delay in VHDL Intertial delay Z <= x after 4 ns; Pulses shorter then 4 ns will be suppressed! Transport delay Z <= transport x after 4 ns; The assignments could be complex Z <= x and y after 4 ns;

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• M. Zwolinski – Digital System Design with VHDL

Testbenches

We want to evaluate correctness of our model Usual way is simulation -> we need stimuli file We have to define a testbench which reads the stimuli, applies this to DUT and checks the results entity TestAnd2 is end entity TestAnd2; architecture io of TestAnd2 is signal a,b,c : BIT; begin g1: entity WORK.And2(ex2) port map (x=>a, y=>b, z=>c); a<= '0', '1' after 100 NS; b<= '0', '1' after 150 NS; end architecture io;

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• M. Zwolinski – Digital System Design with VHDL

Multi-valued Logic

• Example - Three-State Buffer
• We can define the types with different values

type tri is (‘0’,’1’,’Z’); The signal can be then defined as Signal a, b, c: tri;

• How to use tri same as bit signals?

For example how to calculate: B<= a and c after 5 ns;

• Defining the function

AND 1 Z 1 1 1 Z 1 Z

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Standard Logic Type

• Normally the logic implemented in hardware is modelled with more than

binary values (‘0’ and ‘1’) ‘Z’ –high impedance ‘L’ – weak 0 ‘H’ – weak 1 ‘U’ – undefined ‘X’ – strong unknown ‘W’ – weak unknown ‘-’ – don’t care type std_ulogic is (‘U’,’X’,’0’,’1’,’Z’,’W’,’L’,’H’,’-’); How AND truth table for std_ulogic could be defined? subtype std_logic is resolved std_ulogic; Standard types and functions are organized in a package We have to use them from the library library IEEE; use IEEE.std_logic_1164.all;

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Latches

• Difference latch / flip-flop?

Example RS Latch S R Q /Q 1 1 1 1 1 1 1 1 Q /Q

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• M. Zwolinski – Digital System Design with VHDL

VHDL Model of RS-Latch

library IEEE; use IEEE.std_logic_1164.all; entity SR_latch1 is port (S, R : in std_logic; Q, Qbar : buffer std_logic); end entity SR_latch1; architecture dataflow of SR_latch1 is begin Q <= '1' when R = '0' else '0' when S = '0' else Q; Qbar <= '1' when S = '0' else '0' when R = '0' else Qbar; end architecture dataflow;

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• M. Zwolinski – Digital System Design with VHDL

Design of D-Latch

entity dlatch is port (d,en: in std_logic; q: out std_logic); end dlatch; architecture struc of dlatch is begin process (en) begin if en='1' then q<=d; end if; end process; end struc;

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d q en

Design of D-Flip-flop

entity dff is port (d,clk: in std_logic; q: out std_logic); end dff; architecture struc of dff is begin process (clk) begin if clk='1' and clk’event then q<=d; end if; end process; end struc;

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d q clk

Design of D-Flip-flop with asynchronous Reset

entity dff_r is port (d,clk,reset: in std_logic; q: out std_logic); end dff_r; architecture struc of dff_r is begin process (clk, reset) begin if reset=‘1' then q<=‘0’; elsif clk='1' and clk’event then q<=d; end if; end process; end struc;

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d q reset clk

Master-Slave Flip-Flop

Figure source: Wikipedia

Design of D-Flip-flop with asynchronous Set and Reset

entity dff_rs is port (d,clk,setn, resetn: in std_logic; q: out std_logic); end dff_rs; architecture struc of dff_rs is begin process (clk, setn, resetn) begin if resetn=‘0' then q<=‘0’; elsif setn=‘0' then q<=‘1’; elsif clk='1' and clk’event then q<=d; end if; end process; end struc;

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d q setn resetn clk Observe the polarity

• f the control

signals!

Design of D-Flip-flop with synchronous Reset/Set

entity dff_sr is port (d,clk,reset: in std_logic; q: out std_logic); end dff_sr; architecture struc of dff_sr is begin process (clk) begin if clk='1' and clk’event then if reset=‘1' then q<=‘0’; else q<=d; end if; end if; end process; end struc;

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d q reset clk

Timing and Logic checks

Checking metastability as one type of timing check assert condition report message severity level; Severity level: NOTE, WARNING, ERROR, FAILURE

library IEEE; use IEEE.std_logic_1164.all; entity D_FF is generic (Setup, Hold: TIME := 3 ns); port (D, Clk, Set, Reset: in std_logic; Q : out std_logic); begin assert (not(Clk ='1' and Clk'EVENT and not D'STABLE(Setup))) source: www.eet.com report "Setup time violation" severity WARNING; assert (not(Clk ='1' and D'EVENT and not Clk'STABLE(Hold))) report "Hold time violation" severity WARNING; end entity D_FF; architecture behavioural of D_FF is ….

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• M. Zwolinski – Digital System Design with VHDL

Multiple Bit Registers

entity reg16 is generic (n: natural := 16); port (d: in std_logic_vector (n-1 downto 0); clk,reset: in std_logic; q: out std_logic_vector(n-1 downto 0)); end reg16; architecture struc of reg16 is begin process (clk, reset) begin if reset=‘1' then q<=(others =>‘0’); elsif rising_edge(clk) then q<=d; end if; end process; end struc;

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Principles of Synchronous Design

• Pipelined design of the synchronous modules

REGISTER CL REGISTER CL REGISTER clock

Timing of the synchronous design approach

• Clock period
• Setup and hold time
• What is maximal Tclk?
• What is minimal Tclk?

Example – ALU architecture

How synchronous design here functions?

Source: Daniel Gajski, et al, Embedded System Design

Out In1 In2 R2 >>3 >>1 Bus1 abs/max abs/min/+/- Bus2 Bus3 Bus4 R1 R3

Datapath with Chaining

In1 R1 R2 R3 >>1 Bus1 abs/max Bus2 Bus3 Bus4 >>3 In2 Out abs/min/+/-

• Chaining connects two or more FUs
• Allows execution of two or more operation in

a single clock cycle

• Improves performance at no cost

Source: Daniel Gajski, et al, Embedded System Design

In 1 R1 R2 R3 Bus 1 abs/+/- Bus 2 Bus 3 Bus 4 In 2 Out abs/max min >>3 >>1

Datapath with Chained and Multi-Cycled FUs

• Multi-cycling allows use of slower FUs
• Multi-cycling allows faster clock-cycle

Source: Daniel Gajski, et al, Embedded System Design

Pipelining

• Functional Unit pipelining

Two or more operation executing at the same time

• Datapath pipelining

Two or more register transfers executing at the same time

• Control Pipelining

Two or more instructions generated at the same time

Source: Daniel Gajski, et al, Embedded System Design

Functional Unit Pipelining

In1 R1 R2 R3 >>1 Bus1 Bus2 Bus3 Bus4 >>3 In2 Out 2-stage ALU

• Operation delay cut in ”half”
• Shorter clock cycle
• Dependencies may delay some states
• Extra NO states reduce performance gain

Source: Daniel Gajski, et al, Embedded System Design

Datapath Pipelining

In1 R1 R2 R3 >>1 Bus1 Bus2 Bus3 Bus4 >>3 In2 Out ALU

• Register-to-register delay cut in “equal” parts
• Much shorter clock cycle
• Dependencies may delay some states
• Extra NO states reduce performance gain

Source: Daniel Gajski, et al, Embedded System Design

Datapath and Control Pipelining

S1 1 a>b x = c + d y = x - 1 S2 S3 ALU Register Selector RF Mem Bus2 Bus1 Status Signals Control signals

/  

Register

Data Inputs

Datapath

Data Outputs

CWR

PC

CMem AG

SR

Offset

Controller Control Inputs Control Outputs

Bus3

• Fetch delay cut into several parts
• Shorter clock cycle
• Conditionals may delay some states
• Extra NO states reduce performance gain

Source: Daniel Gajski, et al, Embedded System Design

Conclusions

• Here we have shown the principles of VHDL
• How to design combinational circuits
• How to model basic sequential cells
• Principles of synchronous design