ECED2200 Digital Circuits Multiplexor & Demultiplexor - - PowerPoint PPT Presentation

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ECED2200 Digital Circuits Multiplexor & Demultiplexor - - PowerPoint PPT Presentation

ECED2200 Digital Circuits Multiplexor & Demultiplexor 18/07/2012 Colin OFlynn - CC BY-SA 1 General Notes See updates to these slides: www.newae.com/teaching These slides licensed under Creative Commons


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SLIDE 1

ECED2200 – Digital Circuits

Multiplexor & Demultiplexor

18/07/2012 Colin O’Flynn - CC BY-SA 1

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SLIDE 2

General Notes

  • See updates to these slides: www.newae.com/teaching
  • These slides licensed under ‘Creative Commons Attribution-ShareAlike 3.0

Unported License’

  • These slides are not the complete course – they are extended in-class
  • You will find the following references useful, see

www.newae.com/teaching for more information/links:

– The book “Bebop to the Boolean Boogie” which is available to Dalhousie Students – Course notes (covers almost everything we will discuss in class) – Various websites such as e.g.: www.play-hookey.com – The book “Contemporary Logic Design”, which was used in previous iterations of the class and you may have already

18/07/2012 Colin O’Flynn - CC BY-SA 2

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SLIDE 3

Multiplexor/Demultiplexor

18/07/2012 Colin O’Flynn - CC BY-SA 3

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What is a Multiplexor?

18/07/2012 Colin O’Flynn - CC BY-SA 4

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SLIDE 5

2:1 Mux

18/07/2012 Colin O’Flynn - CC BY-SA 5

2:1 Mux

I0 I1 S0 Q0

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SLIDE 6

4:1 Mux

18/07/2012 Colin O’Flynn - CC BY-SA 6

4:1 Mux

I0 I1 S0 Q0 I2 I3 S1

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SLIDE 7

Equations of Mux

18/07/2012 Colin O’Flynn - CC BY-SA 7

S1 S0 Q0 I0 1 I1 1 I2 1 1 I3

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SLIDE 8

8:1 Mux

18/07/2012 Colin O’Flynn - CC BY-SA 8

8:1 Mux

I0 I1 S0 Q0 I2 I3 S1 I4 I5 I6 I7 S2

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Mux as Design Block

18/07/2012 Colin O’Flynn - CC BY-SA 9

A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Mux as Design Block

18/07/2012 Colin O’Flynn - CC BY-SA 10

A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

8:1 Mux

I0 I1 S0 Q0 I2 I3 S1 I4 I5 I6 I7 S2 A B C 1 1 1 1

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SLIDE 11

Mux as a Design Block

18/07/2012 Colin O’Flynn - CC BY-SA 11

8:1 Mux

I0 I1 S0 Y I2 I3 S1 I4 I5 I6 I7 S2 A B C

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SLIDE 12

What is a Demultiplexor?

18/07/2012 Colin O’Flynn - CC BY-SA 12

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2:4 Decoder / Demux

18/07/2012 Colin O’Flynn - CC BY-SA 13

2:4 Decoder

E I0 Q0 I1 Q1 Q2 Q3

2:4 Demux

D S0 Q0 S1 Q1 Q2 Q3 Inputs Address Select

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Notation Information

  • When using ‘Enable’ (tie to ‘1’), we have a
  • decoder. When inputting data, we have

demultiplexor (demux).

  • Naming:

– Decoder/demux named by “control signals:outputs” (e.g.: 2:4) – Mux named by “inputs:outputs” (e.g.: 4:1)

18/07/2012 Colin O’Flynn - CC BY-SA 14

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Decoder as a Design Block

18/07/2012 Colin O’Flynn - CC BY-SA 15

3:8 Decoder

E=‘1’ I0 Q0 I1 Q1 Q2 Q3 I2 Q4 Q5 Q6 Q7 A B C

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Decoder as a Minterm Generator

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3:8 Decoder

E=‘1’ I0 Q0 I1 Q1 Q2 Q3 I2 Q4 Q5 Q6 Q7 A B C

A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C

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TRI-STATE GATES

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Inverter

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3-State Buffer

18/07/2012 Colin O’Flynn - CC BY-SA 19

A E Q 1 1 1 1 Z 1 Z

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Uses for 3-State Buffers

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References

See class notes “Beyond Simple Logic Gates” (page 133)

18/07/2012 Colin O’Flynn - CC BY-SA 21