Shannon decomposition Claude Shannon mathematician / electrical - - PowerPoint PPT Presentation

Shannon decomposition

William Sandqvist william@kth.se

Claude Shannon mathematician / electrical engineer (1916 –2001)

William Sandqvist william@kth.se

(Ex 8.6)

Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function.

William Sandqvist william@kth.se

(Ex 8.6)

Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function. Multiplexer as function generator

William Sandqvist william@kth.se

(Ex 8.6)

=

Show how a 4-to-1 multiplexer can be used as a "function generator" for example to generate the OR function. Multiplexer as function generator

William Sandqvist william@kth.se

William Sandqvist william@kth.se

BV 6.1

Show how the function can be implemented using a 3-to-8 decoder and an OR gate.

∑

= ) 7 , 5 , 4 , 3 , 2 , ( ) , , (

3 2 1

m w w w f

William Sandqvist william@kth.se

BV 6.1

Show how the function can be implemented using a 3-to-8 decoder and an OR gate.

∑

= ) 7 , 5 , 4 , 3 , 2 , ( ) , , (

3 2 1

m w w w f

William Sandqvist william@kth.se

William Sandqvist william@kth.se

Ex 8.7

A majority gate outputs the same value as the majority of the inputs. The gate can for example be used in fault-tolerant logic, or in image processing circuits. a) (Set up the gate's truth table and minimize the function with Karnaugh map. Realize the function with AND-OR gates. ) b) Realize the majority gate with an 8: 1 MUX. c) Use Shannon decomposition and realize the majority gate with a 2: 1 MUX and gates. d) Realize the majority gate with only 2:1 MUXes.

William Sandqvist william@kth.se

(8.7a)

With AND OR gates

William Sandqvist william@kth.se

(8.7a)

With AND OR gates

William Sandqvist william@kth.se

(8.7a)

bc ab ac M + + = With AND OR gates

William Sandqvist william@kth.se

(8.7a)

bc ab ac M + + = With AND OR gates

William Sandqvist william@kth.se

8.7b

With 8-to-1 mux …

William Sandqvist william@kth.se

8.7b

With 8-to-1 mux …

William Sandqvist william@kth.se

8.7c

Shannon decomposition. 2-to-1 mux and gates.

William Sandqvist william@kth.se

8.7c

= + + + = = + + + = ) ( ) ( bc c b c b a bc a abc c ab c b a bc a M Shannon decomposition. 2-to-1 mux and gates.

William Sandqvist william@kth.se

8.7c

= + + + = = + + + = ) ( ) ( bc c b c b a bc a abc c ab c b a bc a M Shannon decomposition. 2-to-1 mux and gates.

William Sandqvist william@kth.se

8.7c

= + + + = = + + + = ) ( ) ( bc c b c b a bc a abc c ab c b a bc a M

OR

Shannon decomposition. 2-to-1 mux and gates.

William Sandqvist william@kth.se

8.7c

= + + + = = + + + = ) ( ) ( bc c b c b a bc a abc c ab c b a bc a M

OR

) ( ) ( c b a bc a + + = Shannon decomposition. 2-to-1 mux and gates.

William Sandqvist william@kth.se

8.7c

= + + + = = + + + = ) ( ) ( bc c b c b a bc a abc c ab c b a bc a M

OR

) ( ) ( c b a bc a + + = Shannon decomposition. 2-to-1 mux and gates.

William Sandqvist william@kth.se

8.7d

Shannon decomposition. Only 2-to-1 muxes.

William Sandqvist william@kth.se

8.7d

1 ) 1 ( ) ( ) ( ) ( ) ( ) ( ⋅ + ⋅ = + + = + + = + + = + = ⋅ + ⋅ = + = + = = + + = b c b c b c b bc b c b c b b b c b h c b b c b b g c b h bc g c b a c b a M Shannon decomposition. Only 2-to-1 muxes.

William Sandqvist william@kth.se

8.7d

1 ) 1 ( ) ( ) ( ) ( ) ( ) ( ⋅ + ⋅ = + + = + + = + + = + = ⋅ + ⋅ = + = + = = + + = b c b c b c b bc b c b c b b b c b h c b b c b b g c b h bc g c b a c b a M Shannon decomposition. Only 2-to-1 muxes.

William Sandqvist william@kth.se

8.7d

1 ) 1 ( ) ( ) ( ) ( ) ( ) ( ⋅ + ⋅ = + + = + + = + + = + = ⋅ + ⋅ = + = + = = + + = b c b c b c b bc b c b c b b b c b h c b b c b b g c b h bc g c b a c b a M Shannon decomposition. Only 2-to-1 muxes.

William Sandqvist william@kth.se

BV 6.5

William Sandqvist william@kth.se

For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. ) 6 , 3 , 2 , ( ) , , (

3 2 1

∑

= m w w w f

BV 6.5

William Sandqvist william@kth.se

For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. ) 6 , 3 , 2 , ( ) , , (

3 2 1

∑

= m w w w f ) ( ) ( ) ( ) ( ) 110 , 011 , 010 , 000 ( ) , , (

3 2 1 3 2 1 3 2 1 3 2 3 2 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1

w w w w w w w w w w w w w w w w w w w w w w w w w w w w m w w w f + + = = + + + = = + + + = = = ∑

BV 6.5

William Sandqvist william@kth.se

For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. ) 6 , 3 , 2 , ( ) , , (

3 2 1

∑

= m w w w f ) ( ) ( ) ( ) ( ) 110 , 011 , 010 , 000 ( ) , , (

3 2 1 3 2 1 3 2 1 3 2 3 2 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1

w w w w w w w w w w w w w w w w w w w w w w w w w w w w m w w w f + + = = + + + = = + + + = = = ∑

BV 6.5

William Sandqvist william@kth.se

For the function use Shannon’s expansion to derive an implementation using a 2-to- 1 multiplexer and any necessary gates. ) 6 , 3 , 2 , ( ) , , (

3 2 1

∑

= m w w w f ) ( ) ( ) ( ) ( ) 110 , 011 , 010 , 000 ( ) , , (

3 2 1 3 2 1 3 2 1 3 2 3 2 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1 3 2 1

w w w w w w w w w w w w w w w w w w w w w w w w w w w w m w w w f + + = = + + + = = + + + = = = ∑

William Sandqvist william@kth.se

William Sandqvist william@kth.se

(Ex 8.9)

Show how one four-input exorgate (XOR, odd parity function) is realized in an FPGA circuit. Show the contents

• f the SRAM cells ( LUT, Lookup

Table )

William Sandqvist william@kth.se

(8.9)

William Sandqvist william@kth.se

(8.9)

William Sandqvist william@kth.se

(8.9)

William Sandqvist william@kth.se

(Ex 8.8)

Set up full adder truth table. Show how a full adder is implemented in an FPGA chip. Logic elements of an FPGA is able to cascade COUT and CIN between "neighbors." Show the contents of the SRAM cells ( LUT, Lookup Table ).

William Sandqvist william@kth.se

(8.8)

William Sandqvist william@kth.se

(8.8)

William Sandqvist william@kth.se

(8.8)

William Sandqvist william@kth.se

(8.8)

William Sandqvist william@kth.se

(BV ex 6.31)

In digital systems it is often necessary to have circuits that can shift the bits of a vector one or more bit positions to the left or right. Design a circuit that can shift a four-bit vector W = w3w2w1w0 one bit position to the right when a control signal Shift is equal to 1. Let the outputs of the circuit be a four-bit vector Y = y3y2y1y0 and a signal k, such that if Shift = 1 then y3 = 0, y2 = w3, y1 = w2, y0 = w1, and k = w0. If Shift = 0 then Y = W and k = 0.

William Sandqvist william@kth.se

William Sandqvist william@kth.se

We uses MUXes:

(BV ex 6.31)

William Sandqvist william@kth.se

(BV ex 6.31)

We uses MUXes:

William Sandqvist william@kth.se

William Sandqvist william@kth.se

BV ex. 6.32 Barrel shifter

The shifter in Example 6.31 shifts the bits of an input vector by one bit position to the right. It fills the vacated bit on the left side with 0. If the bits that are shifted out are placed into the vacated position on the left, then the circuit effectively rotates the bits of the input vector by a specified number of bit positions. Such a circuit is called a barrel shifter. Design a four-bit barrel shifter that rotates the bits by 0, 1, 2, or 3 bit positions as determined by the valuation of two control signals s1 and s0. A barrelshifter is used to speed up floating point operations.

William Sandqvist william@kth.se

Barrel shifter

William Sandqvist william@kth.se

BV ex. 6.32

Truth table:

William Sandqvist william@kth.se

BV ex. 6.32

Truth table:

William Sandqvist william@kth.se

BV ex. 6.32

Truth table:

William Sandqvist william@kth.se

BV ex. 6.32

Truth table:

William Sandqvist william@kth.se

BV ex. 6.32

Truth table:

William Sandqvist william@kth.se

BV ex. 6.32

And so on ... Truth table:

William Sandqvist william@kth.se

= Lowcost FPGA

William Sandqvist william@kth.se

Key Benefits

• Lowest FPGA unit cost starting at

$0.49

• Ultra-low power in Flash*Freeze

mode, as low as 2 µW

• Nonvolatile FPGA eliminates

unnecessary parts from BOM

• Single-chip and ultra-low-power

products simplify board design

• Variety of cost-optimized packages

reduce assembly costs

• Low-power FPGAs reduce thermal

management and cooling needs

William Sandqvist william@kth.se

BV 6.16

Actel Corporation manufactures an FPGA family called Act 1, which uses multiplexer based logic blocks. Show how the function can be implemented using only ACT 1 logic blocks.

3 2 3 1 3 2

w w w w w w f + + =

William Sandqvist william@kth.se

BV 6.16

3 2 3 1 3 2

w w w w w w f + + =

William Sandqvist william@kth.se

BV 6.16

3 2 3 1 3 2

w w w w w w f + + =

( ) ( ) ( ) ( ) ( )

1 2 2 3 2 2 3 1 2 2 3 1 2 1 2 3 2 1 2 1 2 3 2 2 2 1 3 2 1 3 2 2 3 2 3 2 1 3 2 3

1 ) 1 ( 1 ) 1 ( ) ( ) ( ) 1 ( ) ( ) ( ) ( w w w w w w w f w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w f ⋅ + ⋅ + ⋅ + ⋅ = ⋅ + ⋅ = + + = = + + = + + = + ⋅ + ⋅ = + + =

William Sandqvist william@kth.se

BV 6.16

3 2 3 1 3 2

w w w w w w f + + =

( ) ( ) ( ) ( ) ( )

1 2 2 3 2 2 3 1 2 2 3 1 2 1 2 3 2 1 2 1 2 3 2 2 2 1 3 2 1 3 2 2 3 2 3 2 1 3 2 3

1 ) 1 ( 1 ) 1 ( ) ( ) ( ) 1 ( ) ( ) ( ) ( w w w w w w w f w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w f ⋅ + ⋅ + ⋅ + ⋅ = ⋅ + ⋅ = + + = = + + = + + = + ⋅ + ⋅ = + + =

William Sandqvist william@kth.se

BV 6.16

3 2 3 1 3 2

w w w w w w f + + =

( ) ( ) ( ) ( ) ( )

1 2 2 3 2 2 3 1 2 2 3 1 2 1 2 3 2 1 2 1 2 3 2 2 2 1 3 2 1 3 2 2 3 2 3 2 1 3 2 3

1 ) 1 ( 1 ) 1 ( ) ( ) ( ) 1 ( ) ( ) ( ) ( w w w w w w w f w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w w f ⋅ + ⋅ + ⋅ + ⋅ = ⋅ + ⋅ = + + = = + + = + + = + ⋅ + ⋅ = + + =

William Sandqvist william@kth.se

William Sandqvist william@kth.se

VHDL BV 2.51a

Write VHDL code to describe the following functions ) ( ) ( ) (

4 3 2 4 2 1 3 1 2 4 1 2 1 4 3 3 2 3 1 1

x x x x x x x x f x x x x x x x x x x f + + ⋅ + + ⋅ + = + + + + = VHDL code is written with a text editor and saved in a file with the extension.vhd. The code always consists of two sections ENTITY and ARCHITECTURE. Entity is a description of how the circuit "looks from the outside" (the interface), and Architecture how it "looks like inside."

William Sandqvist william@kth.se

VHDL BV 2.51a

) ( ) ( ) (

4 3 2 4 2 1 3 1 2 4 1 2 1 4 3 3 2 3 1 1

x x x x x x x x f x x x x x x x x x x f + + ⋅ + + ⋅ + = + + + + = Comments begin with –- If you wish, you can "draw" clarification ASCII graphics in the comment lines..

• - ___________
• - | |
• - | Functions |
• - ->-| x1 |
• - ->-| x2 f1 |->-
• - ->-| x3 f2 |->-
• - ->-| x4 |
• - |___________|
• Program code is written with a text editor. So we can only do text

comments to the code. A fixed-width font is used ( eg. Courier New ). One usually indent text blocks that belong together for greater clarity.

William Sandqvist william@kth.se

VHDL BV 2.51a

) ( ) ( ) (

4 3 2 4 2 1 3 1 2 4 1 2 1 4 3 3 2 3 1 1

x x x x x x x x f x x x x x x x x x x f + + ⋅ + + ⋅ + = + + + + = ENTITY Functions IS PORT(x1, x2, x3, x4 :IN STD_LOGIC; f1, f2, :OUT STD_LOGIC ) END Functions ARCHITECTURE LogicFunc OF Functions IS BEGIN f1 <= (x1 AND NOT x3)OR(x2 AND NOT x3)OR (NOT x3 AND NOT x4)OR(x1 AND x2)OR (x1 AND NOT x4); f2 <= (x1 OR NOT x3)AND(x1 OR x2 OR NOT x4)AND (x2 OR NOT x3 OR NOT x4); END LogicFunc ;

VHDL BV 6.21

William Sandqvist william@kth.se

Using a selected signal assignement, write VHDL code for a 4-to-2 binary encoder. Only one of w0 …w3 is ”1” at a time. LIBRARY ieee; USE IEEE.std_logic_1164.all; ENTITY ENCODER IS PORT( w :IN STD_LOGIC_VECTOR( 3 DOWNTO 0 ) ; y :OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ) ); END ENCODER ARCHITECTURE Behavior OF ENCODER IS BEGIN WITH w SELECT y <= ”00” WHEN ”0001”, ”01” WHEN ”0010”, ”10” WHEN ”0100”, ”11” WHEN OTHERS; END Behavior ;

William Sandqvist william@kth.se

Additional if time permits

William Sandqvist william@kth.se

Y

• 1

0 1 1 1 1 1

Y

• 1

0 1 1 1 1 1

2 3 3 1 1 2

x x x x x x x x x x Y + + + =

2 3

x x x

3 1

x x x

1x

x

2 x

x

Y

William Sandqvist william@kth.se

Y

• 1

0 1 1 1 1 1

x0 x1 1 0 1

3 2(0,0)

x x ⇒

x0 x1 1 0 1

3 2(0,1)

x x ⇒

x0 x1 1 0 1

3 2(1,1)

x x ⇒

x0 x1 1 0 1

3 2(1,0)

x x ⇒

Y

William Sandqvist william@kth.se

Y

• 1

0 1 1 1 1 1

• 1 0

x0 x1 1 0 1

3 2(0,0)

x x ⇒

0 1 0 1

x0 x1 1 0 1

3 2(0,1)

x x ⇒

0 1 1 0

x0 x1 1 0 1

3 2(1,1)

x x ⇒

• 1 0

x0 x1 1 0 1

3 2(1,0)

x x ⇒

Y

William Sandqvist william@kth.se

Y

• 1

0 1 1 1 1 1

2 3 3 1 1 2

x x x x x x x x x x Y + + + =

• 1 0

x0 x1 1 0 1

2 3

) , ( x Y x x = ⇒

0 1 0 1

x0 x1 1 0 1

2 3

) 1 , ( x Y x x = ⇒

0 1 1 0

x0 x1 1 0 1

1 2 3

) 1 , 1 ( x x Y x x ⊕ = ⇒

• 1 0

x0 x1 1 0 1

2 3

) , 1 ( x Y x x = ⇒

Y

x x x

1

x x ⊕

William Sandqvist william@kth.se

Y

• 1

0 1 1 1 1 1

2 3 3 1 1 2

x x x x x x x x x x Y + + + =

• 1 0

x0 x1 1 0 1

3 2 1

(0,0) x x Y x x ⇒ = ⊕

0 1 0 1

x0 x1 1 0 1

2 3

) 1 , ( x Y x x = ⇒

0 1 1 0

x0 x1 1 0 1

1 2 3

) 1 , 1 ( x x Y x x ⊕ = ⇒

• 1 0

x0 x1 1 0 1

3 2 1

(1,0) x x Y x x ⇒ = ⊕

Y

x

1

x x ⊕

1

x x ⊕

1

x x ⊕

William Sandqvist william@kth.se

Or … Or if you don’t have acess to the variable x0 inverted …

William Sandqvist william@kth.se