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ECED2200 Digital Circuits Karnaugh Maps 16/07/2012 Colin OFlynn - - PowerPoint PPT Presentation

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ECED2200 Digital Circuits Karnaugh Maps 16/07/2012 Colin OFlynn - CC BY-SA 1 General Notes See updates to these slides: www.newae.com/teaching These slides licensed under Creative Commons Attribution-ShareAlike 3.0

  1. ECED2200 – Digital Circuits Karnaugh Maps 16/07/2012 Colin O’Flynn - CC BY-SA 1

  2. General Notes See updates to these slides: www.newae.com/teaching • These slides licensed under ‘Creative Commons Attribution-ShareAlike 3.0 • Unported License’ These slides are not the complete course – they are extended in-class • You will find the following references useful, see • www.newae.com/teaching for more information/links: The book “Bebop to the Boolean Boogie” which is available to Dalhousie Students – Course notes (covers almost everything we will discuss in class) – Various websites such as e.g.: www.play-hookey.com – The book “Contemporary Logic Design”, which was used in previous iterations of the – class and you may have already 16/07/2012 Colin O’Flynn - CC BY-SA 2

  3. Gray Codes 16/07/2012 Colin O’Flynn - CC BY-SA 3

  4. Counters 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 16/07/2012 Colin O’Flynn - CC BY-SA 4

  5. Oops… Bit 3 Bit 2 Bit 1 Bit 0 16/07/2012 Colin O’Flynn - CC BY-SA 5

  6. What are Gray Codes? 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 16/07/2012 Colin O’Flynn - CC BY-SA 6

  7. Generating Gray Codes 0 1 16/07/2012 Colin O’Flynn - CC BY-SA 7

  8. Generating Gray Codes 3-bit Gray Code 3. 2. 2. 3. 1. 1. 00 000 0 0 00 00 01 001 1 1 01 01 11 011 11 1 11 10 010 10 0 10 10 110 2-bit Gray Code 111 11 1. Write known Gray code down, even just 1-bit Gray Code 101 01 2. Mirror Gray code vertically 3. Add a single ‘0’ infront of original code, 100 00 add a single ‘1’ infront of mirrored code 4. Repeat until required # of bits made 16/07/2012 Colin O’Flynn - CC BY-SA 8

  9. MINIMIZATION BY MAPPING 16/07/2012 Colin O’Flynn - CC BY-SA 9

  10. Karnaugh Maps A B C Minterms f Invented by Maurice Karnaugh 0 0 0 0 0 0 1 0 0 1 0 0 AB m = 00 01 11 10 A•B•C 0 1 1 1 C 3 0 1 1 m = 1 0 0 1 A•B•C 1 1 1 1 4 m = 1 0 1 1 A•B•C 5 m = 1 1 0 1 A•B•C 6 m = 1 1 1 1 A•B•C 7 = + + + + f m m m m m 3 4 5 6 7 16/07/2012 Colin O’Flynn - CC BY-SA 10

  11. Karnaugh (K-Map) Minimization 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 11

  12. Karnaugh (K-Map) Minimization 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 12

  13. K-Map: 3-Input Product of Sum A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C 16/07/2012 Colin O’Flynn - CC BY-SA 13

  14. K-Map: 4-Inputs Product of Sum A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D 16/07/2012 Colin O’Flynn - CC BY-SA 14

  15. Mapping Connections 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 15

  16. Mapping Connections ( ) ( ) Y= A•D + B•C 1 1 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 16

  17. Mapping Connections 1 1 Y=B•D 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 17

  18. Mapping Connections 16/07/2012 Colin O’Flynn - CC BY-SA 18

  19. Notes on Grouping Terms 1. Groups must consist of 1,2,4,8,16,.. Etc terms 2. Left & Right-Side of K-Maps Connect 3. Top & Bottom of K-Maps Connect 4. Try to maximize number of terms per group 5. There may be multiple solutions to same problem 6. Based on if more 1’s or 0’s in truth table can use Product-of-Sum or Sum-of-Product resp. 16/07/2012 Colin O’Flynn - CC BY-SA 19

  20. Multiple Solutions 16/07/2012 Colin O’Flynn - CC BY-SA 20

  21. Example #1 – Vote Taker Map the following: A B C Y 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 21

  22. A B C Y Example #1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C 16/07/2012 Colin O’Flynn - CC BY-SA 22

  23. Example #2 – Full Adder A B Cin Sum Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 23

  24. Example #2 – Full Adder A B Cin Sum 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 A B Cin Cout 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 24

  25. Example #3 – Comparator A B C D AB > CD 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 16/07/2012 Colin O’Flynn - CC BY-SA 25

  26. Example #3 - Comparator 16/07/2012 Colin O’Flynn - CC BY-SA 26

  27. Mapping with Don’t Cares A B C Y 0 0 0 0 0 0 1 0 0 1 0 ? 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 ? 16/07/2012 Colin O’Flynn - CC BY-SA 27

  28. Mapping with Don’t Cares A B C Y 0 0 0 0 0 0 1 0 0 1 0 ? 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 ? 16/07/2012 Colin O’Flynn - CC BY-SA 28

  29. Note on Don’t Care Notation 16/07/2012 Colin O’Flynn - CC BY-SA 29

  30. Product of Sum Mapping A B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 30

  31. Mapping using SoP A B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 31

  32. Mapping using PoS A B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 16/07/2012 Colin O’Flynn - CC BY-SA 32

  33. Mapping 5 Input Variables E=1 E=0 16/07/2012 Colin O’Flynn - CC BY-SA 33

  34. Checking your Results http://k-map.sourceforge.net 16/07/2012 Colin O’Flynn - CC BY-SA 34

  35. Section Summary • See ECED2200 Notes “Minimization By Mapping” (Page 76) • Bebop to the Boolean Boogie Chapter 10 • Contemporary Logic Design Chapter 2 Useful software: http://k-map.sourceforge.net/ 16/07/2012 Colin O’Flynn - CC BY-SA 35

  36. MAPPING EQUATIONS 16/07/2012 Colin O’Flynn - CC BY-SA 36

  37. A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C 16/07/2012 Colin O’Flynn - CC BY-SA 37

  38. A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D 16/07/2012 Colin O’Flynn - CC BY-SA 38

  39. Section Summary • See ECED2200 Notes “Minimization By Mapping” (Page 76) • Bebop to the Boolean Boogie Chapter 10 • Contemporary Logic Design Chapter 2 16/07/2012 Colin O’Flynn - CC BY-SA 39

  40. NAND – NOR CONVERSIONS 16/07/2012 Colin O’Flynn - CC BY-SA 40

  41. FET Logic Gates - NAND Source: http://commons.wikimedia.org/wiki/File:NAND_gate_(CMOS_circuit).PNG 16/07/2012 Colin O’Flynn - CC BY-SA 41

  42. FET Logic Gates - NOR http://commons.wikimedia.org/wiki/File:NOR_gate_%28CMOS_circuit%29.PNG 16/07/2012 Colin O’Flynn - CC BY-SA 42

  43. Equivalencies • A+B A B • A+B A B  A B A+B • A+B A B 16/07/2012 Colin O’Flynn - CC BY-SA 43

  44. NAND Conversion: Step 1 1. Draw complete schematic 16/07/2012 Colin O’Flynn - CC BY-SA 44

  45. NAND Conversion: Step 2 Convert all AND gates to NAND gates and add additional inverted input to next level: 16/07/2012 Colin O’Flynn - CC BY-SA 45

  46. NAND Conversion: Step 3 Convert all OR gates to NAND gates: 16/07/2012 Colin O’Flynn - CC BY-SA 46

  47. NAND Conversion: Step 4 If two circles connect together cancel them. If circles do not cancel on inputs to NAND gates, add inverter built from NAND. 16/07/2012 Colin O’Flynn - CC BY-SA 47

  48. Section Summary • See ECED2200 Notes “Conversion to NAND and NOR Networks” (Page 102) 16/07/2012 Colin O’Flynn - CC BY-SA 48

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