ECED2200 Digital Circuits Karnaugh Maps 16/07/2012 Colin OFlynn - - - PowerPoint PPT Presentation

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ECED2200 Digital Circuits Karnaugh Maps 16/07/2012 Colin OFlynn - - - PowerPoint PPT Presentation

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ECED2200 Digital Circuits Karnaugh Maps 16/07/2012 Colin OFlynn - CC BY-SA 1 General Notes See updates to these slides: www.newae.com/teaching These slides licensed under Creative Commons Attribution-ShareAlike 3.0

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SLIDE 1

ECED2200 – Digital Circuits

Karnaugh Maps

16/07/2012 Colin O’Flynn - CC BY-SA 1

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SLIDE 2

General Notes

  • See updates to these slides: www.newae.com/teaching
  • These slides licensed under ‘Creative Commons Attribution-ShareAlike 3.0

Unported License’

  • These slides are not the complete course – they are extended in-class
  • You will find the following references useful, see

www.newae.com/teaching for more information/links:

– The book “Bebop to the Boolean Boogie” which is available to Dalhousie Students – Course notes (covers almost everything we will discuss in class) – Various websites such as e.g.: www.play-hookey.com – The book “Contemporary Logic Design”, which was used in previous iterations of the class and you may have already

16/07/2012 Colin O’Flynn - CC BY-SA 2

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SLIDE 3

Gray Codes

16/07/2012 Colin O’Flynn - CC BY-SA 3

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SLIDE 4

Counters

16/07/2012 Colin O’Flynn - CC BY-SA 4

1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000

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SLIDE 5

Oops…

16/07/2012 Colin O’Flynn - CC BY-SA 5

Bit 3 Bit 2 Bit 1 Bit 0

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SLIDE 6

What are Gray Codes?

0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111

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SLIDE 7

Generating Gray Codes

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1

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SLIDE 8

Generating Gray Codes

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1 1 1 00 01 11 10

1. 2. 3.

00 01 11 10 00 01 11 10 10 11 01 00 000 001 011 010 110 111 101 100

1. 2. 3. 3-bit Gray Code 2-bit Gray Code

  • 1. Write known Gray code down, even just

1-bit Gray Code

  • 2. Mirror Gray code vertically
  • 3. Add a single ‘0’ infront of original code,

add a single ‘1’ infront of mirrored code

  • 4. Repeat until required # of bits made
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SLIDE 9

MINIMIZATION BY MAPPING

16/07/2012 Colin O’Flynn - CC BY-SA 9

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SLIDE 10

Karnaugh Maps

16/07/2012 Colin O’Flynn - CC BY-SA 10

Invented by Maurice Karnaugh A B C Minterms f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

3 4 5 6 7

f m m m m m = + + + +

4

A•B•C m =

5

A•B•C m =

6

A•B•C m =

7

A•B•C m =

3

A•B•C m =

AB C 00 01 11 10 1 1 1 1 1 1

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SLIDE 11

Karnaugh (K-Map) Minimization

16/07/2012 Colin O’Flynn - CC BY-SA 11

1 1 1 1 1

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SLIDE 12

Karnaugh (K-Map) Minimization

16/07/2012 Colin O’Flynn - CC BY-SA 12

1 1 1 1 1

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SLIDE 13

K-Map: 3-Input Product of Sum

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A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C

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SLIDE 14

K-Map: 4-Inputs Product of Sum

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A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D

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SLIDE 15

Mapping Connections

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1 1 1 1

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SLIDE 16

Mapping Connections

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1 1 1 1 1 1 1

( ) ( )

Y= A•D + B•C

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SLIDE 17

Mapping Connections

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1 1 1 1

Y=B•D

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SLIDE 18

Mapping Connections

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SLIDE 19

Notes on Grouping Terms

  • 1. Groups must consist of 1,2,4,8,16,.. Etc terms
  • 2. Left & Right-Side of K-Maps Connect
  • 3. Top & Bottom of K-Maps Connect
  • 4. Try to maximize number of terms per group
  • 5. There may be multiple solutions to same

problem

  • 6. Based on if more 1’s or 0’s in truth table can

use Product-of-Sum or Sum-of-Product resp.

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SLIDE 20

Multiple Solutions

16/07/2012 Colin O’Flynn - CC BY-SA 20

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SLIDE 21

Example #1 – Vote Taker

Map the following:

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A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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SLIDE 22

Example #1

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A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C

A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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SLIDE 23

Example #2 – Full Adder

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A B Cin Sum Cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Example #2 – Full Adder

16/07/2012 Colin O’Flynn - CC BY-SA 24 A B Cin Sum 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A B Cin Cout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Example #3 – Comparator

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A B C D AB > CD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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SLIDE 26

Example #3 - Comparator

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Mapping with Don’t Cares

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A B C Y 1 1 ? 1 1 1 1 1 1 1 1 1 1 1 1 1 ?

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SLIDE 28

Mapping with Don’t Cares

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A B C Y 1 1 ? 1 1 1 1 1 1 1 1 1 1 1 1 1 ?

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SLIDE 29

Note on Don’t Care Notation

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Product of Sum Mapping

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A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Mapping using SoP

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A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Mapping using PoS

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A B C Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Mapping 5 Input Variables

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E=0 E=1

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SLIDE 34

Checking your Results

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http://k-map.sourceforge.net

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Section Summary

  • See ECED2200 Notes “Minimization By

Mapping” (Page 76)

  • Bebop to the Boolean Boogie Chapter 10
  • Contemporary Logic Design Chapter 2

Useful software: http://k-map.sourceforge.net/

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SLIDE 36

MAPPING EQUATIONS

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SLIDE 37

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A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C A•B•C

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SLIDE 38

16/07/2012 Colin O’Flynn - CC BY-SA 38

A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D A•B•C•D

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SLIDE 39

Section Summary

  • See ECED2200 Notes “Minimization By

Mapping” (Page 76)

  • Bebop to the Boolean Boogie Chapter 10
  • Contemporary Logic Design Chapter 2

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SLIDE 40

NAND – NOR CONVERSIONS

16/07/2012 Colin O’Flynn - CC BY-SA 40

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SLIDE 41

FET Logic Gates - NAND

Source: http://commons.wikimedia.org/wiki/File:NAND_gate_(CMOS_circuit).PNG

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SLIDE 42

FET Logic Gates - NOR

http://commons.wikimedia.org/wiki/File:NOR_gate_%28CMOS_circuit%29.PNG

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Equivalencies

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A+B A B

  • A B

 A+B A B

  • A+B

A+B A B

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NAND Conversion: Step 1

  • 1. Draw complete schematic

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NAND Conversion: Step 2

Convert all AND gates to NAND gates and add additional inverted input to next level:

16/07/2012 Colin O’Flynn - CC BY-SA 45

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NAND Conversion: Step 3

Convert all OR gates to NAND gates:

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NAND Conversion: Step 4

If two circles connect together cancel them. If circles do not cancel on inputs to NAND gates, add inverter built from NAND.

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Section Summary

  • See ECED2200 Notes “Conversion to NAND

and NOR Networks” (Page 102)

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