[PPT] - Data Concentrator SVD data multiplexer with FPGA-based tracking PowerPoint Presentation

SLIDE 1

Data Concentrator

SVD data multiplexer with FPGA-based tracking Tracking-Meeting Bayrischzell Jochen Dingfelder, Carlos Mariñas, Michael Schnell schnell@physik.uni-bonn.de

University of Bonn

July, 19th 2012

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 1 / 21

SLIDE 2

Content

1

Motivation

2

Hardware Status

3

FPGA-based tracking

4

Simulation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 2 / 21

SLIDE 3

Motivation

Copper System Data Concentrator

ROI

ptical links

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 3 / 21

SLIDE 4

Hardware Status

Content

1

Motivation

2

Hardware Status

3

FPGA-based tracking

4

Simulation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 4 / 21

SLIDE 5

Hardware Status

Hardware Solution

Advanced Mezzanine Card (AMC)
Redesign with 4 SFP connectors

(Zhen-An) → 11 cards

Received during DEPFET meeting

in Seeon

Given back to Zhen-An for fixing

backplane problems

Start testing, when it returns

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 5 / 21

SLIDE 6

Hardware Status

Simplified Block Diagram

FD FD FD FD

4:1 Mux

FD FD FD FD

4:1 Mux

Framer

11:1 Mux

FD FD FD FD

4:1 Mux

Decoder Scheduler & MMU 4 GB DDR 2 Memory

Track reconstruction

Ethernet Frame GPU Protocol Framer Amplitude Analysis Collection AMC "Datcon"

ATCA GPU Farm

FD FD FD Framer Framer

. . .

AMC "Collector"

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 6 / 21

SLIDE 7

FPGA-based tracking

Content

1

Motivation

2

Hardware Status

3

FPGA-based tracking

4

Simulation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 7 / 21

SLIDE 8

FPGA-based tracking

Data Flow Diagram Plan

General tracking module interconnection (can also be distributed)

Conformal transformation SVD strip-data Coordinate translator Hough transformation ROI creator Track creation Intercept finder ATCA

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 8 / 21

SLIDE 9

FPGA-based tracking

Coordinate Translation

LUT for basic location lookup of each ladder With strip ID, strip pitch in u-v direction and DSP of FPGA determine precise position Alignment constant for each ladder in u-v direction Constant for sagging correction with LUT of a x2 function

Start Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 9 / 21

SLIDE 10

FPGA-based tracking

SVD Clustering idea

+ Take center and size of cluster, saves space and resources − Additional type of data needed

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 10 / 21

SLIDE 11

FPGA-based tracking

General Testing Platform

Userland

track generation and strip ID calculation

Kernel

transmission to PCIe

ver DMA map

PCIe 1x

transmission to FPGA and init processing

FPGA

processing and back transmission

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 11 / 21

SLIDE 12

Simulation

Content

1

Motivation

2

Hardware Status

3

FPGA-based tracking

4

Simulation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 12 / 21

SLIDE 13

Simulation

Real 2D Hit

500 Background hits (∼ 1 percent occupancy) 5 generated tracks

0.2
0.15
0.1
0.05

0.05 0.1 0.15 0.2

0.2
0.15
0.1
0.05

0.05 0.1 0.15 0.2 y x Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 13 / 21

SLIDE 14

Simulation

Hough Space

Corresponding Hough Space:

30
20
10

10 20 30

1.5
1
0.5

0.5 1 1.5 d φ

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 14 / 21

SLIDE 15

Simulation

FHT Example With Less Background

30 background hits and 2 tracks in Hough space

30
20
10

10 20 30

1.5
1
0.5

0.5 1 1.5 d φ

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 15 / 21

SLIDE 16

Simulation

FHT Example With Less Background

30 background hits and 2 tracks in Hough space with intercept regions

30
20
10

10 20 30

1.5
1
0.5

0.5 1 1.5 d φ

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 15 / 21

SLIDE 17

Simulation

FHT Example With Less Background

Zoom to one of the intercept regions

1.35
1.3
1.25
1.2
1.15
1.1
1.05
1.28
1.278
1.276
1.274
1.272
1.27
1.268

d φ

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 15 / 21

SLIDE 18

Simulation

Definitions

A few later used definitions: Efficiency: ǫ := number of correct found tracks

total number of real tracks

ǫ ∈ [0, 1] → For all later shown plots: ǫ = 1!! Purity: p :=

number of found tracks total number of real tracks

p ≥ 0 → p ≥ 1

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 16 / 21

SLIDE 19

Simulation

Track Purity With FPGA Algorithm Simulation

0.8 1 1.2 1.4 1.6 1.8 2 100 150 200 300 400 500 # reconstructed tracks / # generated tracks Background Hits 1 generated Track 2 generated Tracks 3 generated Tracks 4 generated Tracks 5 generated Tracks Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 17 / 21

SLIDE 20

Simulation

Execution Time

Running on Core i7 2600 @ 3.8 GHz (with fixed affinity + turbo boost):

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 100 200 300 400 500 600 700 800 900 1000 Time [s] Hits Create Hough Trafo Intercept Finder Intercept Finder (Vertex constrained)

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 18 / 21

SLIDE 21

Simulation

Visualization Software

For visualization full VXD (SVD, PXD) with active area and strip and pixel structure Marking background, tracks, clusters... Presentation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 19 / 21

SLIDE 22

Simulation

Summary and Status

2D Simulation of the SVD (r-ϕ plane only), r-z plane in progress Track reconstruction efficiency is high, but...

tracks with Gaussian smearing only (2 strip pitches) No multiple scattering, energy loss, magnetic field inhomogeneities...

→ Switch to the basf2 framework

Done, but only with local coordinates of sensors.
Hough transformation only feasible with up to 1 − 2 percent
ccupancy

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 20 / 21

SLIDE 23

Simulation

Thank you for your attention!

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 24

Backup Technical Specifications

Technical Specification on I/O

Input:

Up to 42 (32)

ptical-fibre links

1.5 Gbps max On average 110 Mbps expected Dynamic bandwidth

Output:

6.25 Gbps over backplane or SFP+ 440 Mbps average data rate

→ Total: 4.6 Gbps ≈ 550 MiB/s

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 25

Backup Idea

Tracking Options

Hough Transformation to find straight and arc tracks (after conformal transformation) Can be fast and efficient implemented in the FPGA over Fast Hough Transformation (FHT) First 2D resulsts of the next slides Open for other algorithm, like sector-neighbour finding cellular automaton or Kalman-Filter

1
0.5

0.5 1 0.5 1 1.5 2 a m 0.5 1 1.5 2 2.5 3 3.5 4 0.5 1 1.5 2 2.5 3 3.5 4 y x

Hough transformation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 26

Backup FPGA Implementation

Trigonometric Functions and Memory Requirements

Need trigonometric functions like sine and cosine e.g. for coordinate transformation CORDIC: Basic Lookup table for nodes and a shift-add implementation of approximation function Pure LUT: Large Lookup table for every value (high memory requirements) FPGAs’ DSPs used as Multiplier/Divider unit. Block Memory needed to translate strip IDs into coordinates and ROI creation

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 27

Backup FPGA Implementation

Status of the Different Blocks in Simulations

FD FD FD FD

4:1 Mux

FD FD FD FD

4:1 Mux

Framer

11:1 Mux

FD FD FD FD

4:1 Mux

Decoder Scheduler & MMU 4 GB DDR 2 Memory

Track reconstruction

Ethernet Frame GPU Protocol Framer Amplitude Analysis Collection AMC "Datcon"

ATCA GPU Farm

FD FD FD Framer Framer

. . .

AMC "Collector"

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 28

Backup Multiplexer Theory

Multiplexing

Three general types of multiplexing:

Frequency Division Multiplexing (FDM) Time Division Multiplexing (TDM) Statistical Multiplexing

Because of dynamic bandwidth “Statistical Multiplexing” would be most suitable Demultiplexing is trivial, if only multiplexing of 32 bit words is ensured

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 29

Backup Multiplexer Theory

Aurora overview

Xilinx Aurora protocol as physical link layer over GTP Takes care of every “low level” operation like clock correction, symbol decoding and 8B/10B Encoding Easy data transmission/framing over locallink Error detection and initialization Status wires for channel and lanes Lane: One communication line Channel: Concentration of one or more lanes

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 30

Backup Hough-Transformation

Simple Hough Trafo in 2D with straight tracks

Hits in 2 D Want to find straight tracks i: yi = m · xi + a in this mess → Go to Hough-Space: a = −m · xi + yi

0.5 1 1.5 2 2.5 3 3.5 4 0.5 1 1.5 2 2.5 3 3.5 4 y x

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 22 / 21

SLIDE 31

Backup Hough-Transformation

Hough-Space

1
0.5

0.5 1 0.5 1 1.5 2 a m

Find interception of 5 Tracks around zero! Found 2: y1 = 0.6 · x; y2 = 1.5 · x

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 32

Backup Hough-Transformation

With tracks

Found 2: y1 = 0.6 · x y2 = 1.5 · x

0.5 1 1.5 2 2.5 3 3.5 4 0.5 1 1.5 2 2.5 3 3.5 4 y x tr 1 tr 2

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 33

Backup Hough-Transformation

Coordinate Transformation

This is bad for tracks close or parallel to y-axes (m = inf.)! Make a coordinate transformation like: r = x · cos(Φ) + y · sin(Φ)

0.5 1 1.5 2 0.5 1 1.5 2 y x track

r

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 34

Backup Hough-Transformation

Implementation in FPGA?

Use Fast Hough Transformation! Divide and Conquer type algorithm

1
0.5

0.5 1 0.5 1 1.5 2 a m

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 35

Backup Hough-Transformation

Implementation in FPGA 2

Vary with minimum and maximum size of a unit area the tolerance Efficient and highly parallelisable, a sector for each unit

1
0.5

0.5 1 0.5 1 1.5 2 a m

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 36

Backup Hough-Transformation

Implementation in FPGA 3

Also support of different shapes One more to go...

1
0.5

0.5 1 0.5 1 1.5 2 a m

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21

SLIDE 37

Backup Hough-Transformation

Implementation in FPGA 4

Error comes for “free” Done... finally

1
0.5

0.5 1 0.5 1 1.5 2 a m

Michael Schnell (University of Bonn) Data Concentrator July, 19th 2012 21 / 21