CENG 342 Digital Systems A Combinational Logic Circuit in VHDL - PowerPoint PPT Presentation

CENG 342 – Digital Systems A Combinational Logic Circuit in VHDL Larry Pyeatt SDSM&T

Testbench VHDL code can be simulated in a computer to verify the correctness. After simulation, the code can be synthesized to a physical device. For simulation, a special program, called a testbench , is created to mimic a physical lab bench. The uut block is the unit under test. The test vector generator block generates testing input patterns. The monitor observes the output. The testbench is a VHDL entity with no ports. There is a tutorial on the course website for using the Xilinx Vivado to create and simulate VHDL code.

Testbench code 1 LIBRARY ieee; 21 begin 2 USE ieee.std_logic_1164.ALL; -- Instantiate the Unit Under Test 22 uut: comparator_for_1bit PORT MAP ( 3 23 4 ENTITY cmp_testbench IS i0 => i0, 24 5 END cmp_testbench; i1 => i1, 25 6 26 eq => eq 7 ARCHITECTURE behavior OF cmp_testbench IS 27 ); 8 -- Component Declaration for the 28 -- Stimulus process 9 -- Unit Under Test (UUT) 29 stim_proc: process 10 COMPONENT comparator_for_1bit 30 begin 11 PORT( 31 -- hold reset state for 100 ns. 12 i0 : IN std_logic; 32 wait for 100 ns; 13 i1 : IN std_logic; 33 i0 <= not i0; 14 eq : OUT std_logic 34 wait for 100 ns; 15 ); 35 i1 <= not i1; 16 END COMPONENT; 36 wait for 100 ns; --Inputs i0 <= not i0; 17 37 signal i0 : std_logic := ’0’; end process; 18 38 signal i1 : std_logic := ’0’; 39 END; 19 signal eq : std_logic; 20 In a process, the statements are evaluated sequentially. (Imperative programming.)

Wait Since processes are imperative programming, control structures may be needed. We will cover them as we need them. The wait statement is used to suspend a process Wait for time period Example: wait for 20ns; Wait until Boolean-expression: suspends a process until the expression becomes TRUE Example: wait until falling_edge(clk); Wait on sensitivity-list: wait until one of the signals on the sensitivity list changes Example: wait on max_tick; Wait by itself will suspend the process indefinitely Example: wait; --suspend process for remainder of simulation

For Loop The for loop defines a loop parameter which takes on the type of the range specified. Examples: for I in 0 to 3 loop 1 -- loop body 2 end loop; 3 1 type PRIMARY is (RED, GREEN, BLUE); 2 ... for SEL in PRIMARY loop 3 -- loop body 4 end loop; 5 Attributes such as ’high , ’low and ’range may also be used to define the iterations of a for loop: TMP := ’0’; 1 for I in A’low to A’high loop 2 TMP := TMP xor A(I); 3 end loop; 4 ODD <= TMP; 5 We will discuss attributes in more detail later.

Modeling Styles Structural Modeling describes a set of interconnected components by declaring their existence and connections. The component instantiation statements are concurrent in nature, so the order of these statements is not important. For example, the following statement blocks are equivalent; 1 and1: entity work.and(behavioral) 1 or1: entity work.or(behavioral) 2 port map(i0=>a, i1=>b, o=>ab); 2 port map(i0=>ab, i1=>bc, o=>f); 3 and2: entity work.and(behavioral) 3 and2: entity work.and(behavioral) 4 port map(i0=>b, i1=>c, o=>bc); 4 port map(i0=>b, i1=>c, o=>bc); 5 or1: entity work.or(behavioral) 5 and1: entity work.and(behavioral) 6 port map(i0=>ab, i1=>bc, o=>f); 6 port map(i0=>a, i1=>b, o=>ab); Dataflow Modeling defines a set of concurrent (parallel) statements which declare the relationships between signals. The signal assignment statements are concurrent in nature, so the order of these statements is not important. For example, the following statement blocks are equivalent; 1 eq <= p0 or p1; 1 p1 <= i0 and i1; 2 p0 <= (not i0) and (not i1); 2 p0 <= (not i0) and (not i1); 3 p1 <= i0 and i1; 3 eq <= p0 or p1;

Modeling Styles - Continued Behavioral Modeling describes the functionality (or behavior) of an entity using sequential statements. These statements are usually specified within a process statement. The process statement itself is a concurrent statement, but inside it lies a set of statements which are all sequential in nature. Their order is important. Mixed Modeling is the combination of any of the three pure modeling styles.

2-bit Comparator a 1 a 0 b 1 b 0 a = b 0 0 0 0 1 0 0 0 1 0 Logical function for a = b ? 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1

2-bit Comparator a 1 a 0 b 1 b 0 a = b 0 0 0 0 1 0 0 0 1 0 Logical function for a = b ? 0 0 1 0 0 0 0 1 1 0 00 01 11 10 0 1 0 0 0 1 0 0 0 00 0 1 0 1 1 0 1 0 0 01 0 1 1 0 0 0 0 1 0 11 0 1 1 1 0 0 0 0 1 10 1 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1

2-bit Comparator a 1 a 0 b 1 b 0 a = b 0 0 0 0 1 0 0 0 1 0 Logical function for a = b ? 0 0 1 0 0 0 0 1 1 0 00 01 11 10 0 1 0 0 0 1 0 0 0 00 0 1 0 1 1 0 1 0 0 01 0 1 1 0 0 0 0 1 0 11 0 1 1 1 0 0 0 0 1 10 1 0 0 0 0 1 0 0 1 0 Not much simplification possible there. . . 1 0 1 0 1 f = a 1 a 0 b 1 b 0 + a 1 a 0 b 1 b 0 + a 1 a 0 b 1 b 0 + a 1 a 0 b 1 b 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1

2-bit Comparator: VHDL Entity Declaration Here is the entity declaration: 1 library IEEE; 2 use IEEE.std_logic_1164.ALL; 3 4 -- eq2 is a two-bit comparator. 5 -- If a==b then aeqb=1, else aeqb=0 6 entity eq2 is Port ( a : in std_logic_vector (1 downto 0); 7 b : in std_logic_vector (1 downto 0); 8 aeqb : out std_logic); 9 10 end eq2; We use std_logic_vector for each of the two inputs. This allows us to define them as two-bit busses. When defining std_logic_vector , we typically put the highest index on the left, which goes along with our concept that the bits in a multi-bit number are counted up from right to left (or down from left to right). This declares an entity which accepts two 2-bit numbers, and outputs a single bit. It does not say what the relationship is between the inputs and the outputs. That part is done in the architecture. We leave a comment here so that we know what it does without reading the code in the architecture(s).

2-bit Comparator: VHDL Data Flow Implementation With the previous Sum-Of-Products equation, we can create a straightforward Data Flow implementation: 12 architecture sop_arch of eq2 is signal p0,p1,p2,p3: std_logic; 13 14 begin 15 -- sum of product terms 16 aeqb <= p0 or p1 or p2 or p3; 17 -- product terms 18 p0 <= ((not a(1)) and (not b(1))) and ((not a(0)) and (not b(0))); 19 p1 <= ((not a(1)) and (not b(1))) and (a(0) and b(0)); 20 p2 <= (a(1) and b(1)) and ((not a(0)) and (not b(0))); 21 p3 <= (a(1) and b(1)) and (a(0) and b(0)); 22 end sop_arch; This collection of concurrent statements describes the logical relationship between the signals and ports in the device. (A port is a special type of signal.)

2-bit Comparator: VHDL Structural Implementation Structural design allows us to build a large system from simple building blocks. It is close to schematic capture. Components are interconnected in a hierarchical manner. Structural descriptions may connect simple gates or complex, abstract components. We can use the 1-bit comparator to build a 2-bit comparator. Graphical representation: a 0 a 0 = b 0 eq 1 b 0 a = b a 1 eq 1 b 1 a 1 = b 1 VHDL: 24 architecture struc_arch of eq2 is signal e0, e1: std_logic; 25 26 begin 27 -- instantiate two 1-bit comparators 28 eq_bit0_unit: entity work.eq1(sop_arch) port map(i0=>a(0), i1=>b(0), eq=>e0); 29 eq_bit1_unit: entity work.eq1(sop_arch) port map(i0=>a(1), i1=>b(1), eq=>e1); 30 -- a and b are equal if individual bits are equal 31 aeqb <= e0 and e1; 32 end struc_arch; Note that this is actually a mixed model implementation.

Entity Instantiation Syntax: 1 unit_label: entity lib_name.entity_name (arch_name) port map (formal_signal => actual_signal , ... ); 2 The work library is the default library to store the compiled entity and architecture units. The port mapping specifies the connections, where formal_signal is the I/O port in a component entity (building block), while actual_signal is a signal or port on the entity you are defining. For structural design of VHDL, put all relevant source files under the same project. Create a project 1 Add a VHDL source file for the 1-bit comparator. 2 3 Create a testbench file for the 1-bit comparator (should be in “simulation only” sources). Do simulation and check the correctness. 4 Under the same project (hardware chip icon xcs400), create a new VHDL source file for the 2-bit comparator. 5 Under the same project, create a new VHDL source file for the testbench for the 2-bit comparator (should be in “simulation only” sources). Do simulation and check the correctness.

Component Instantiation