CENG 342 – Digital Systems Algorithmic State Machine with Datapath (ASMD) Larry Pyeatt SDSM&T
Finite State Machine – Review Any Finite state machine with two inputs, two Mealy outputs, two Moore outputs, and up to four states can be expressed graphically as this: Combinational Inputs Logic Circuit (Next State) Memory Devices (Flip−Flops) Combinational Logic Circuit Moore Outputs (Moore Outputs) Combinational Logic Circuit Mealy Outputs (Mealy Outputs)
FSM – Review Finite state machines may be described in more detail using a state diagram. The state diagram is a graph, which means that it is composed of a set of nodes and a set of arcs. Each node has a set of incoming arcs and a set of outgoing arcs. Moore outputs are associated with nodes. Mealy outputs are associated with arcs. The following diagram shows a single node with one incoming arc and two outgoing arcs. MO: Moore output Logical expression {/ ME ← value {, . . . }} ME: Mealy output State_Name MO ← value . . . Logical expression {/ ME ← value {, . . . }} Logical expression {/ ME ← value {, . . . }} To other state To other state
FSM – Review MO: Moore output Logical expression {/ ME ← value {, . . . }} ME: Mealy output State_Name MO ← value . . . Logical expression {/ ME ← value {, . . . }} Logical expression {/ ME ← value {, . . . }} To other state To other state Each node has a list of Moore outputs, which are asserted whenever that state is the current state. Each arc has a Logical Expression, which specifies the condition under which that arc is taken, and a set of Mealy Outputs, which are asserted whenever that condition becomes true in the state represented by the source node. We often define “default” values for both Moore and Mealy outputs. If a value is not explicitly listed, then the default value is assumed.
FSM – Review Example from “The Designer’s Guide to VHDL.” – An FSM with both Mealy and Moore outputs: S 0 ab / y 0 ← 1 a a S 1 S 2 a y 1 ← 1
FSM – VHDL Implementation A methodical approach makes it much easier and less error-prone. Use the VHDL enumerated data type to represent the states. Use three section coding method: 1 A process which updates the current state. 2 A process or concurrent statement(s) to generate the next state. A process or concurrent statement(s) to generate the outputs. 3
FSM – VHDL Implementation 1 library ieee; 2 use ieee.std_logic_1164.all; S 0 3 4 entity fsm_eg is port( 5 ab / y 0 ← 1 clk, reset: in std_logic; 6 a a a, b : in std_logic; 7 y0, y1 : out std_logic; 8 ); 9 S 1 S 2 a 10 end fsm_eg; y 1 ← 1 11 12 architecture mult_seg_arch of fsm_eg is type eg_state_type is (s0, s1, s2); 13 signal state_reg, state_next : eg_state_type; 14 15 begin Combinational Inputs Logic Circuit (Next State) -- state update 16 process(clk,reset) 17 Memory begin 18 Devices (Flip−Flops) 19 if reset = ’1’ then -- asynchronous reset state_reg <= s0; 20 Combinational elsif rising_edge(clk) then Logic Circuit Moore Outputs 21 (Moore Outputs) state_reg <= state_next; 22 end if; 23 Combinational Logic Circuit Mealy Outputs end process; 24 (Mealy Outputs)
FSM – VHDL Implementation -- next state logic 26 process (state_reg, a, b) S 0 27 begin 28 case state_reg is 29 when s0 => 30 ab / y 0 ← 1 if a = ’1’ then 31 a a if b = ’1’ then 32 state_next <= s2; 33 else 34 S 1 S 2 a state_next <= s1; 35 y 1 ← 1 end if; 36 else 37 state_next <= s0; 38 end if; 39 when s1 => Combinational 40 Inputs Logic Circuit (Next State) if a = ’1’ then 41 state_next <= s0; 42 Memory else 43 Devices (Flip−Flops) 44 state_next <= s1; end if; 45 Combinational when s2 => Logic Circuit Moore Outputs 46 (Moore Outputs) state_next <= s0; 47 end case; 48 Combinational Logic Circuit Mealy Outputs end process; 49 (Mealy Outputs)
FSM – VHDL Implementation -- Moore output logic 51 process(state_reg) 52 S 0 begin 53 case state_reg is 54 when s0 | s2 => 55 56 y1 <= ’0’; ab / y 0 ← 1 when s1 => 57 a a y1 <= ’1’; 58 end case; 59 end process; 60 S 1 S 2 a 61 y 1 ← 1 -- Mealy output logic 62 process(state_reg,a,b) 63 begin 64 case state_reg is 65 when s0 => 66 Combinational Inputs Logic Circuit if a = ’1’ and b = ’1’ then (Next State) 67 y0 <= ’1’; 68 Memory else 69 Devices (Flip−Flops) y0 <= ’0’; 70 end if; 71 Combinational Logic Circuit when s1 | s2 => Moore Outputs 72 (Moore Outputs) y0 <= ’0’; 73 end case; 74 Combinational Logic Circuit Mealy Outputs end process (Mealy Outputs) 75 76 end mult_seg_arch;
FSM – VHDL Implementation Much simpler implementation of output logic: S 0 ab / y 0 ← 1 a a -- Moore output logic 78 S 1 S 2 y1 <= ’1’ when state_reg = s1 else ’0’; a 79 y 1 ← 1 80 81 -- Mealy output logic 82 y0 <= ’1’ when (state_reg = s0 83 and a =’1’ 84 Combinational Inputs Logic Circuit and b = ’1’) else ’0’; (Next State) 85 Memory Devices (Flip−Flops) Combinational Logic Circuit Moore Outputs (Moore Outputs) Combinational Logic Circuit Mealy Outputs (Mealy Outputs)
Example – Edge Detector Moore Mealy level level ZERO ZERO level level level / tick ← 1 level EDGE ONE tick ← 1 level level level The zero and one states indicate that the input signal has been 0 or 1 ONE For a while level
FSMD Finite state machine with datapath Uses an FSM to drive another sequential circuit Data Routing Functional Routing Data Data Input Output Network Units Network Register(s) Internal Status Control Signals Next State State Output Status Logic Register Logic Output Command
Register Transfer Level The FSMD is used to implement systems that are described at the Register Transfer Level (RTL). An RT operation specifies data manipulation and transfer for a single destination register. Example: r dest ← f ( r src 1 , r src 2 , . . . , r src n ) Elementary operations are called microoperations . Some examples are: load: r x ← r y , count: r x ← r x + C where C is a constant, shift: r x ← lsl ( r x , amt ) , bitwise “or”: r x ← r x ∨ r y , etc. There is a fairly well established syntax for RTL operations. You can extend the syntax, if you explain what your operations mean, and be consistent.
Common RTL Syntax The ← symbol indicates data transfer into a register. R 1 ← R 2 Brackets [] specify an operation on memory. The memory address goes inside the brackets, and the memory device name precedes the brackets. R 0 ← M [ AR ] M [ AR ] ← R 5 A comma is used to separate parallel operations. r x ← r y , r a ← r b + r c A colon specifies a condition under which the transfer occurs. K 1 : r x ← r y , r a ← r b + r c ab : r x ← r x + 1
RTL It is assumed that all RT operations are synchronized by a shared clock. The results from the operation are not stored until the next rising (or falling, if you design it that way) edge of the clock. The following figures show two ways to achieve the same results. The figure on the left takes one clock cycle to get the result. The one on the right takes two clock cycles, but is more flexible. It uses a “routing network” shown previously. Can you design a circuit that can perform the unified a − b + 1 operation in one clock cycle, but is also capable of performing either the a − b or the a + 1 operation individually? a ← a − b a ← a + 1 a ← a − b + 1 + 1 + 1 d q d q − a a − clk clk d q d q b b clk clk
Algorithmic State Machine For designing the state machine, it is often easier to use an Algorithmic State Machine (ASM) chart. The ASM chart is a network of ASM blocks. State blocks represent the states and Moore outputs. Decision blocks represent condition tests. Conditional output blocks represent Mealy outputs. Decision Block State 0 1 Condition State Block Moore Expression Outputs Mealy Conditional Output Block Outputs
Algorithmic State Machine ASM with datapath The clock is assumed to drive state transitions. The ASM chart specifies operations that must be implemented by the datapath. s0 r1 ← 8 s1 << 2 8 r1 ← r1 + r2 d q r1 + clk s2 r1 ← r1 << 2 d q r2 clk s3 r1 ← r1
Algorithmic State Machine It is common to use one or more multiplexers as a routing network to provide input to the registers and/or the functional units. The following ASM chart is equivalent to one circle in the state diagram. The dashed lines show an ASM block. The clock causes transition from one ASM block to the next. Some decision nodes can be handled completely within the datapath. s0 r1 ← r1 − 1 − 1 d q r1 en F T a > b + d q a r2 r2 ← r2 + b r2 ← r2 + a b en a > b Control Signals
ASMD Timing The destination register(s) get updated when exiting the current ASMD block, but not within the block. Each ASMD block represents one clock cycle. There can be errors when that fact is forgotten. s1 s1 s1 r_next := r − 1 r ← r − 1 r ← r_next r ← r_next F T F T r = 0 r_next ← r − 1 r_next = 0 F T The := symbol can r_next = 0 be used to specify a local signal that is assigned immediatly
State Diagram and ASM Equivalence s0 S 0 F a = 1 T ab / y 0 ← 1 F T a a b = 1 y0 ← 1 S 1 S 2 a s1 s2 y 1 ← 1 y1 ← 1 T F a = 1
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