CENG 342 Digital Systems Routing Circuits Larry Pyeatt SDSM&T - PowerPoint PPT Presentation

CENG 342 – Digital Systems Routing Circuits Larry Pyeatt SDSM&T

Routing Circuit Concurrent assignment statements: Conditional signal assignment and Selected signal assignment Instead of being executed sequentially, statements are mapped to a routing network during synthesis Conditional signal assignment 1 r <= a+b+c when m=n else a-b when m>n else 2 c+1; 3 Boolean expressions must be mutually exclusive and all inclusive The routing is done by a 2-to-1 multiplexer.

Conditional Signal Assignment Statement

Priority Encoder Input: four requests r 4 , r 3 , r 2 , and r 1 . r 4 has the highest priority. Output: the 3-bit binary code of the highest-priority request. For example, if r 4 = 0, r 3 = 1, r 2 = 1, and r 1 = 0, output should be “011”. r 4 r 3 r 2 r 1 f 2 f 1 f 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 Truth table: 0 0 1 - 0 1 0 0 1 - - 0 1 1 1 - - - 1 0 0 VHDL code 1 library ieee; 10 2 use ieee.std_logic_1164.all; 11 architecture cond_arch of prio_encoder is 3 12 begin 4 entity prio_encoder is 13 f <= "100" when (r(4)=’1’) else 5 port( 14 "011" when (r(3)=’1’) else 6 r: in std_logic_vector(4 downto 1); 15 "010" when (r(2)=’1’) else 7 f: out std_logic_vector(2 downto 0) 16 "001" when (r(1)=’1’) else ); "000"; 8 17 9 end prio_encoder; 18 end cond_arch;

Binary Decoder An n -to-2 n decoder has an n -bit input and 2 n outputs. The n inputs represent a binary number that determines which output is true. A 2-to-4 decoder with enable operates according to the following truth table. en a 1 a 0 Q 0 Q 1 Q 2 Q 3 0 - - 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 VHDL code 1 library ieee; 11 2 use ieee.std_logic_1164.all; 12 architecture cond_arch of decoder_2_4 is 3 13 begin 4 entity decoder_2_4 is y <= "0000" when (en=’0’) else 14 port( 5 "0001" when (a="00") else 15 a: in std_logic_vector(1 downto 0); 6 "0010" when (a="01") else 16 en: in std_logic; 7 "0100" when (a="10") else 17 y: out std_logic_vector(3 downto 0) 8 "1000"; 18 ); 9 19 end cond_arch; 10 end decoder_2_4;

Selected Signal Assignment Statement Similar to a case statement. 4-to-1 multiplexer with sel as the selection signal selection signal: 1 signal sel: std_logic_vector(1 downto 0) 2 ... 3 with sel select r<= a+b+c when "00", 4 a-b when "10", 5 c+1 when others; 6 All possible values of sel must be covered by one and only one choice. others should be used at the end to cover unused and/or unsynthesizable values such as ’X’ . All choices must be mutually exclusive and all inclusive

Selected Signal Assignment Statement – continued The selected signal assignment implies a multiplexing structure 1 signal sel: std_logic_vector(1 downto 0) 2 ... 3 with sel select r<= a+b+c when "00", 4 a-b when "10", 5 c+1 when others; 6 a+b+c a-b c+1

Priority Encoder (2 nd approach) Priority encodeer using selected signal assignment statement. r 4 r 3 r 2 r 1 f 2 f 1 f 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 - 0 1 0 0 1 - - 0 1 1 1 - - - 1 0 0 20 architecture sel_arch of prio_encoder is 21 begin with r select 22 f <= "100" when "1000"|"1001"|"1010"|"1011"|"1100"|"1101"|"1110"|"1111", 23 "011" when "0100"|"0101"|"0110"|"0111", 24 25 "010" when "0010"|"0011", 26 "001" when "0001", 27 "000" when others; 28 end sel_arch;

Binary Decoder (2 nd approach) Binary decoder using selected signal assignment statement. en a 1 a 0 Q 0 Q 1 Q 2 Q 3 0 - - 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 21 architecture sel_arch of decoder_2_4 is 22 signal s: std_logic_vector(2 downto 0); 23 begin s <= en & a; 24 with s select 25 y <= "0000" when "000"|"001"|"010"|"011", 26 "0001" when "100", 27 "0010" when "101", 28 "0100" when "110", 29 "1000" when others; 30 31 end sel_arch;