CENG 342 Digital Systems Routing Circuits Larry Pyeatt SDSM&T - - PowerPoint PPT Presentation

CENG 342 – Digital Systems

Routing Circuits Larry Pyeatt

SDSM&T

Routing Circuit

Concurrent assignment statements: Conditional signal assignment and Selected signal assignment Instead of being executed sequentially, statements are mapped to a routing network during synthesis Conditional signal assignment

1 r <= a+b+c when m=n else 2

a-b when m>n else

3

c+1; Boolean expressions must be mutually exclusive and all inclusive The routing is done by a 2-to-1 multiplexer.

Conditional Signal Assignment Statement

Priority Encoder

Input: four requests r4, r3, r2, and r1. r4 has the highest priority. Output: the 3-bit binary code of the highest-priority

• request. For example, if r4 = 0, r3 = 1, r2 = 1, and r1 = 0, output should be “011”.

Truth table:

r4 r3 r2 r1 f2 f1 f0 1 1 1

• 1

1

• 1

1 1

• 1

VHDL code

1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity prio_encoder is 5

port(

6

r: in std_logic_vector(4 downto 1);

7

f: out std_logic_vector(2 downto 0)

8

);

9 end prio_encoder; 10 11 architecture cond_arch of prio_encoder is 12 begin 13

f <= "100" when (r(4)=’1’) else

14

"011" when (r(3)=’1’) else

15

"010" when (r(2)=’1’) else

16

"001" when (r(1)=’1’) else

17

"000";

18 end cond_arch;

Binary Decoder

An n-to-2n decoder has an n-bit input and 2n outputs. The n inputs represent a binary number that determines which output is true. A 2-to-4 decoder with enable operates according to the following truth table.

en a1 a0 Q0 Q1 Q2 Q3

• 1

1 1 1 1 1 1 1 1 1 1 1

VHDL code

1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity decoder_2_4 is 5

port(

6

a: in std_logic_vector(1 downto 0);

7

en: in std_logic;

8

y: out std_logic_vector(3 downto 0)

9

);

10 end decoder_2_4; 11 12 architecture cond_arch of decoder_2_4 is 13 begin 14

y <= "0000" when (en=’0’) else

15

"0001" when (a="00") else

16

"0010" when (a="01") else

17

"0100" when (a="10") else

18

"1000";

19 end cond_arch;

Selected Signal Assignment Statement

Similar to a case statement. 4-to-1 multiplexer with sel as the selection signal selection signal:

1 signal sel: std_logic_vector(1 downto 0) 2 ... 3 with sel select 4

r<= a+b+c when "00",

5

a-b when "10",

6

c+1 when others; All possible values of sel must be covered by one and only one choice.

• thers should be used at the end to cover unused and/or unsynthesizable values such

as ’X’. All choices must be mutually exclusive and all inclusive

Selected Signal Assignment Statement – continued

The selected signal assignment implies a multiplexing structure

1 signal sel: std_logic_vector(1 downto 0) 2 ... 3 with sel select 4

r<= a+b+c when "00",

5

a-b when "10",

6

c+1 when others;

a+b+c a-b c+1

Priority Encoder (2nd approach)

Priority encodeer using selected signal assignment statement.

r4 r3 r2 r1 f2 f1 f0 1 1 1

• 1

1

• 1

1 1

• 1

20 architecture sel_arch of prio_encoder is 21 begin 22

with r select

23

f <= "100" when "1000"|"1001"|"1010"|"1011"|"1100"|"1101"|"1110"|"1111",

24

"011" when "0100"|"0101"|"0110"|"0111",

25

"010" when "0010"|"0011",

26

"001" when "0001",

27

"000" when others;

28 end sel_arch;

Binary Decoder (2nd approach)

Binary decoder using selected signal assignment statement.

en a1 a0 Q0 Q1 Q2 Q3

• 1

1 1 1 1 1 1 1 1 1 1 1

21 architecture sel_arch of decoder_2_4 is 22

signal s: std_logic_vector(2 downto 0);

23 begin 24

s <= en & a;

25

with s select

26

y <= "0000" when "000"|"001"|"010"|"011",

27

"0001" when "100",

28

"0010" when "101",

29

"0100" when "110",

30

"1000" when others;

31 end sel_arch;