CENG 342 Digital Systems Sign-magnitude Adder Larry Pyeatt - - PowerPoint PPT Presentation

CENG 342 – Digital Systems

Sign-magnitude Adder Larry Pyeatt

SDSM&T

Inattention Blindness

How many Red Points do you see in the picture? 5 or 6?

Inattention Blindness

How many Red Points do you see in the picture? 5 or 6? How many fingers does the man have?

Sign-magnitude adder

Sign-magnitude format: the MSB is the sign and the remaining is the magnitude, for example 410 = 01002 and −410 = 11002. Operation of sign-magnitude adder

If the two operands have the same sign, add the magnitude and keep the sign If the two operands have different signs, subtract the smaller magnitude from the larger one and keep the larger one’s sign

Two-stage design

Sort two input numbers according to amplitude (max, min) Perform regular addition or subtraction depending on the signs

VHDL

No carry-out is considered in the following sign-magnitude adder. Think about how to modify the code to include carry-out.

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity sign_mag_add is 6

generic(N: integer:=4); -- default 4 bits

7

port(

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a, b: in std_logic_vector(N-1 downto 0);

9

sum: out std_logic_vector(N-1 downto0)

10

);

11 end sign_mag_add;

VHDL – continued

13 architecture arch of sign_mag_add is 14

signal mag_a, mag_b: unsigned(N-2 downto 0);

15

signal mag_sum, max, min: signed(N-2 downto 0);

16

signal sign_a, sign_b, sign_sum:std_logic;

17 begin 18

mag_a <= unsigned(a(N-2 downto 0));

19

mag_b <= unsigned(b(N-2 downto 0));

20

sign_a <= a(N-1);

21

sign_b <= b(N-1);

22

• - sort according to magnitude

23

process(mag_a,mag_b,sign_a,sign_b)

24

begin

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if mag_a > mag_b then

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max <= mag_a;

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min <= mag_b;

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sign_sum <= sign_a;

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else

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max <= mag_b;

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min <= mag_a;

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sign_sum <= sign_b;

33

end if;

34

end process;

35 -- add/sub magnitude 36

mag_sum <= max + min when sign_a=sign_max - min;

37 -- final output 38

sum <= std_logic_vector(sign_sum & mag_sum);

39 end arch;

Testing Circuit

Use 8 switches to enter 2 input numbers, the sign and magnitude are shown on 1 seven-segment LEDs, respectively. Both the operand and sum can be shown to the LED display. Two push buttons serves as the selection signal of a mux to route an operand or sum to the LED display The rightmost LED shows the magnitude and the next show the sign, blank for positive sign and "-" for negative sign.

VHDL

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 entity sm_add_test is 5

port(

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clk: in std_logic;

7

btn: in std_logic_vector(1 downto 0);

8

sw: in std_logic_vector(7 downto 0);

9

an: out std_logic_vector(3 downto 0);

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sseg: out std_logic_vector(7 downto 0)

11

);

12 end sm_add_test; 13 14 architecture arch of sm_add_test is 15

signal sum, mout, oct: std_logic_vector(3 downto 0);

16

signal led3, led2, led1, led0:

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std_logic_vector(7 downto 0);

18 begin 19

• - instantiate adder

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sm_adder_unit: entity work.sign_mag_add

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generic map(N=>4)

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port map(a=>sw(3 downto 0), b=>sw(7 downto 4),

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sum=>sum);

VHDL – continued

24

• - 4-to-1 mux to select a number to display

25

with btn select

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mout <= sw(3 downto 0) when "00", -- a

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sw(7 downto 4) when "01", -- b

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sum when others; -- sum

29

• - magnitude displayed on rightmost 7-seg LED

30

• ct <= ’0’ & mout(2 downto 0); --since magnitude has 3 bits, add a 0 in front

31

sseg_unit: entity work.hex_to_sseg

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port map(hex=>oct, dp=>’0’, sseg=>led0);

33

• - sign displayed on 2nd 7-seg LED, note here hex-sseg module is not needed

34

• - we can simply assign a desired value

35

led1 <= "11111110" when mout(3)=’1’ else -- middle bar is lit

36

"11111111"; -- blank

37

• - other two 7-seg LEDs blank (note they are configured active-low, so all 1s

38

• - indicate blank)

39

led2 <= "11111111";

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led3 <= "11111111";

41 -- instantiate display multiplexer 42

disp_unit: entity work.disp_mux

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port map(

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clk=>clk, reset=>’0’,

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in0=>led0, in1=>led1, in2=>led2, in3=>led3,

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an=>an, sseg=>sseg);

47 end arch;