CENG 342 Digital Systems Sign-magnitude Adder Larry Pyeatt - PowerPoint PPT Presentation

CENG 342 – Digital Systems Sign-magnitude Adder Larry Pyeatt SDSM&T

Inattention Blindness How many Red Points do you see in the picture? 5 or 6?

Inattention Blindness How many Red Points do you see in the picture? 5 or 6? How many fingers does the man have?

Sign-magnitude adder Sign-magnitude format: the MSB is the sign and the remaining is the magnitude, for example 4 10 = 0100 2 and − 4 10 = 1100 2 . Operation of sign-magnitude adder If the two operands have the same sign, add the magnitude and keep the sign If the two operands have different signs, subtract the smaller magnitude from the larger one and keep the larger one’s sign Two-stage design Sort two input numbers according to amplitude (max, min) Perform regular addition or subtraction depending on the signs

VHDL No carry-out is considered in the following sign-magnitude adder. Think about how to modify the code to include carry-out. 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity sign_mag_add is generic(N: integer:=4); -- default 4 bits 6 port( 7 a, b: in std_logic_vector(N-1 downto 0); 8 sum: out std_logic_vector(N-1 downto0) 9 ); 10 11 end sign_mag_add;

VHDL – continued 13 architecture arch of sign_mag_add is signal mag_a, mag_b: unsigned(N-2 downto 0); 14 signal mag_sum, max, min: signed(N-2 downto 0); 15 signal sign_a, sign_b, sign_sum:std_logic; 16 17 begin mag_a <= unsigned(a(N-2 downto 0)); 18 mag_b <= unsigned(b(N-2 downto 0)); 19 sign_a <= a(N-1); 20 sign_b <= b(N-1); 21 -- sort according to magnitude 22 23 process(mag_a,mag_b,sign_a,sign_b) begin 24 if mag_a > mag_b then 25 max <= mag_a; 26 min <= mag_b; 27 sign_sum <= sign_a; 28 else 29 max <= mag_b; 30 min <= mag_a; 31 sign_sum <= sign_b; 32 end if; 33 end process; 34 35 -- add/sub magnitude mag_sum <= max + min when sign_a=sign_max - min; 36 37 -- final output sum <= std_logic_vector(sign_sum & mag_sum); 38 39 end arch;

Testing Circuit Use 8 switches to enter 2 input numbers, the sign and magnitude are shown on 1 seven-segment LEDs, respectively. Both the operand and sum can be shown to the LED display. Two push buttons serves as the selection signal of a mux to route an operand or sum to the LED display The rightmost LED shows the magnitude and the next show the sign, blank for positive sign and "-" for negative sign.

VHDL 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 entity sm_add_test is port( 5 clk: in std_logic; 6 btn: in std_logic_vector(1 downto 0); 7 sw: in std_logic_vector(7 downto 0); 8 an: out std_logic_vector(3 downto 0); 9 sseg: out std_logic_vector(7 downto 0) 10 ); 11 12 end sm_add_test; 13 14 architecture arch of sm_add_test is signal sum, mout, oct: std_logic_vector(3 downto 0); 15 signal led3, led2, led1, led0: 16 std_logic_vector(7 downto 0); 17 18 begin -- instantiate adder 19 sm_adder_unit: entity work.sign_mag_add 20 generic map(N=>4) 21 port map(a=>sw(3 downto 0), b=>sw(7 downto 4), 22 sum=>sum); 23

VHDL – continued -- 4-to-1 mux to select a number to display 24 with btn select 25 mout <= sw(3 downto 0) when "00", -- a 26 sw(7 downto 4) when "01", -- b 27 sum when others; -- sum 28 -- magnitude displayed on rightmost 7-seg LED 29 oct <= ’0’ & mout(2 downto 0); --since magnitude has 3 bits, add a 0 in front 30 sseg_unit: entity work.hex_to_sseg 31 port map(hex=>oct, dp=>’0’, sseg=>led0); 32 -- sign displayed on 2nd 7-seg LED, note here hex-sseg module is not needed 33 -- we can simply assign a desired value 34 led1 <= "11111110" when mout(3)=’1’ else -- middle bar is lit 35 "11111111"; -- blank 36 -- other two 7-seg LEDs blank (note they are configured active-low, so all 1s 37 -- indicate blank) 38 led2 <= "11111111"; 39 led3 <= "11111111"; 40 41 -- instantiate display multiplexer disp_unit: entity work.disp_mux 42 port map( 43 clk=>clk, reset=>’0’, 44 in0=>led0, in1=>led1, in2=>led2, in3=>led3, 45 an=>an, sseg=>sseg); 46 47 end arch;