CENG 342 Digital Systems Hexadecimal Digit to Seven-segment LED - PowerPoint PPT Presentation

CENG 342 – Digital Systems Hexadecimal Digit to Seven-segment LED Decoder Larry Pyeatt SDSM&T

7-segment LED display A 7-segment LED is configured active low (segment is lit when the control signal is ’0’). Why? 4-bit input as a hexadecimal digit 8-bit output (including decimal point dp )

VHDL The hex-to-7-segment driver can be implemented in VHDL with two statements. 12 architecture arch of hex_to_sseg is 13 begin 14 with hex select sseg(6 downto 0) <= 15 "0000001" when "0000", 16 "1001111" when "0001", 17 1 library ieee; "0010010" when "0010", 18 2 use ieee.std_logic_1164.all; "0000110" when "0011", 19 "1001100" when "0100", 3 20 4 entity hex_to_sseg is "0100100" when "0101", 21 port( "0100000" when "0110", 5 22 hex: in std_logic_vector(3 downto 0); "0001111" when "0111", 6 23 dp: in std_logic; "0000000" when "1000", 7 24 sseg: out std_logic_vector(7 downto 0) "0000100" when "1001", 8 25 ); "0001000" when "1010", --a 9 26 10 end hex_to_sseg; "1100000" when "1011", --b 27 "0110001" when "1100", --c 28 "1000010" when "1101", --d 29 "0110000" when "1110", --e 30 "0111000" when others; --f 31 sseg(7) <= dp; 32 33 end arch;

Testing Circuit Use 7-segment LED displays on the S3 board Add a user constraint file ( .ucf ) Use four switches as input Use 7-segment LED as output Testing results: Switches: “0011” Switches: “1111” Switches: “0001” The Nexys A7 is similar, but has 8 hex displays instead of four.

Time-multiplexing The Nexys A7 and the S3 board both use a time-multiplexing scheme for the 7-segment displays. The each digit has an individual enable signal, but they all share the eight common signals to control which segments are illuminated. Thus, we can can enable one display at a time, rather than all at once. Use a state machine to cycle through the digits. I you switch between them at 60Hz or higher, it fools the human eye into thinking they are all on constantly.

Time-multiplex the LED displays enabling each display in turn. The refresh rate of an is fast enough. It seems like all four displays are lit simultaneously and display different patterns. We can play lots of tricks on the human eye:

Implementation disp_mux will be introduced in a later slide. For the time being we can treat this as a black block. Example: 1 ... -- instantiate 7-seg LED display time-multiplexing module 2 disp_unit: entity work.disp_mux 3 port map(clk=>clk, reset=>’0’, 4 in0=>led0, in1=>led1, in2=>led2, in3=>led3, 5 an=>an, sseg=>sseg); 6 7 end arch;

Testing Circuit Use four 7-segment LED displays on the board. sw is the 8-bit switch of the board. It is fed to an increment to obtain sw+1 . Nybbles of sw and sw+1 are passed to 4 decoders to display 4 hexadecimal digits on four 7-segment LED displays.

VHDL 1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity hex_to_sseg_test is port( -- user constraint file connects: 6 clk: in std_logic; -- connect to clock on board 7 sw:in std_logic_vector(7 downto 0); -- connect to switches 8 an:out std_logic_vector(3 downto 0); -- connect to 7-segment enables 9 sseg:out std_logic_vector(7 downto 0) -- connect to 7-segment segs 10 ); 11 12 end hex_to_sseg_test; 13 14 architecture arch of hex_to_sseg_test is signal inc:std_logic_vector(7 downto 0); 15 signal led3, led2, led1, led0: 16 17 std_logic_vector(7downto 0); 18 19 begin 20 -- increment input (type conversion!) 21 inc <= std_logic_vector(unsigned(sw) + 1); 22 -- instantiate four instances of hex decoders 23 -- instance for 4 LSBs of input 24 sseg_unit_0: entity work.hex_to_sseg 25 port map(hex=>sw(3 downto 0), dp =>’1’, 26 sseg=>led0);

VHDL – continued 27 -- instance for 4 MSBs of input sseg_unit_1: entity work.hex_to_sseg 28 port map(hex=>sw(7 downto 4), dp =>’1’, 29 sseg=>led1); 30 31 -- instance for 4 LSBs of incremented value sseg_unit_2: entity work.hex_to_sseg 32 port map(hex=>inc(3 downto 0), dp =>’0’, 33 sseg=>led2); 34 35 -- instance for 4 MSBs of incremented value sseg_unit_3: entity work.hex_to_sseg 36 port map(hex=>inc(7 downto 4), dp =>’1’, 37 sseg=>led3); 38 39 -- instantiate 7-seg LED display -- 40 --time-multiplexing module 41 disp_unit: entity work.disp_mux 42 port map( 43 clk=>clk, reset=>’0’, 44 in0=>led0, in1=>led1, 45 in2=>led2, in3=>led3, 46 an=>an, sseg=>sseg); 47 end arch;

Testing Result

The generate Statement Allows the programmer to instantiate an “array” of entities/components. Syntax: 1 label: for parameter in range generate concurrent statements 2 3 end generate label; The generate parameter may be used to index array-type signals associated with component ports. Example: 1 architecture GEN of REG_BANK is component REG 2 port(D,CLK,RESET : in std_ulogic; 3 Q : out std_ulogic); 4 end component; 5 6 begin GEN_REG: 7 for I in 0 to 3 generate 8 REGX : REG port map 9 (DIN(I), CLK, RESET, DOUT(I)); 10 end generate GEN_REG; 11 12 end GEN;

VHDL using generate 14 architecture gen of hex_to_sseg_test is 15 signal inc:std_logic_vector(7 downto 0); 16 signal alldisp:std_logic_vector(15 downto 0); 17 signal led3, led2, led1, led0: 18 std_logic_vector(7 downto 0); 19 signal allled:std_logic_vector(31 downto 0); 20 begin 21 -- increment input (type conversion!) 22 inc <= std_logic_vector(unsigned(sw) + 1); 23 -- generate four instances of hex decoders 24 alldisp <= sw & inc; -- combine all hex data to make generate easier 25 allled <= led3 & led2 & led1 & led0; -- combine led lines 26 for i in 0 to 3 generate 27 DECX : entity work.hex_to_sseg_test 28 port map(hex=>alldisp(((i*4)+3) downto (i*4) ), dp =>’1’, 29 sseg=>allled((i*8)+7 downto (1*8))); 30 end generate DECX; 31 32 33 -- instantiate 7-seg LED display -- 34 --time-multiplexing module disp_unit: entity work.disp_mux 35 port map( 36 clk=>clk, reset=>’0’, 37 in0=>allled(7 downto 0), in1=>alled(15 downto 8), 38 in2=>allled(23 downto 16), in3=>alled(31 downto 24), 39 an=>an, sseg=>sseg); 40 41 end arch;