CENG 342 Digital Systems Hexadecimal Digit to Seven-segment LED - - PowerPoint PPT Presentation

CENG 342 – Digital Systems

Hexadecimal Digit to Seven-segment LED Decoder Larry Pyeatt

SDSM&T

7-segment LED display

A 7-segment LED is configured active low (segment is lit when the control signal is ’0’). Why? 4-bit input as a hexadecimal digit 8-bit output (including decimal point dp)

VHDL

The hex-to-7-segment driver can be implemented in VHDL with two statements.

1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity hex_to_sseg is 5

port(

6

hex: in std_logic_vector(3 downto 0);

7

dp: in std_logic;

8

sseg: out std_logic_vector(7 downto 0)

9

);

10 end hex_to_sseg; 12 architecture arch of hex_to_sseg is 13 begin 14

with hex select

15

sseg(6 downto 0) <=

16

"0000001" when "0000",

17

"1001111" when "0001",

18

"0010010" when "0010",

19

"0000110" when "0011",

20

"1001100" when "0100",

21

"0100100" when "0101",

22

"0100000" when "0110",

23

"0001111" when "0111",

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"0000000" when "1000",

25

"0000100" when "1001",

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"0001000" when "1010", --a

27

"1100000" when "1011", --b

28

"0110001" when "1100", --c

29

"1000010" when "1101", --d

30

"0110000" when "1110", --e

31

"0111000" when others; --f

32

sseg(7) <= dp;

33 end arch;

Testing Circuit

Use 7-segment LED displays on the S3 board Add a user constraint file (.ucf)

Use four switches as input Use 7-segment LED as output

Testing results: Switches: “0001” Switches: “0011” Switches: “1111” The Nexys A7 is similar, but has 8 hex displays instead of four.

Time-multiplexing

The Nexys A7 and the S3 board both use a time-multiplexing scheme for the 7-segment displays. The each digit has an individual enable signal, but they all share the eight common signals to control which segments are illuminated. Thus, we can can enable one display at a time, rather than all at once. Use a state machine to cycle through the digits. I you switch between them at 60Hz or higher, it fools the human eye into thinking they are all on constantly.

Time-multiplex the LED displays enabling each display in turn. The refresh rate of an is fast enough. It seems like all four displays are lit simultaneously and display different patterns. We can play lots of tricks on the human eye:

Implementation

disp_mux will be introduced in a later slide. For the time being we can treat this as a black block. Example:

1 ... 2

• - instantiate 7-seg LED display time-multiplexing module

3

disp_unit: entity work.disp_mux

4

port map(clk=>clk, reset=>’0’,

5

in0=>led0, in1=>led1, in2=>led2, in3=>led3,

6

an=>an, sseg=>sseg);

7 end arch;

Testing Circuit

Use four 7-segment LED displays on the board. sw is the 8-bit switch of the board.

It is fed to an increment to obtain sw+1. Nybbles of sw and sw+1 are passed to 4 decoders to display 4 hexadecimal digits on four 7-segment LED displays.

VHDL

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity hex_to_sseg_test is 6

port(

• - user constraint file connects:

7

clk: in std_logic;

• connect to clock on board

8

sw:in std_logic_vector(7 downto 0);

• connect to switches

9

an:out std_logic_vector(3 downto 0);

• connect to 7-segment enables

10

sseg:out std_logic_vector(7 downto 0) -- connect to 7-segment segs

11

);

12 end hex_to_sseg_test; 13 14 architecture arch of hex_to_sseg_test is 15

signal inc:std_logic_vector(7 downto 0);

16

signal led3, led2, led1, led0:

17

std_logic_vector(7downto 0);

18 19 begin 20 -- increment input (type conversion!) 21

inc <= std_logic_vector(unsigned(sw) + 1);

22 -- instantiate four instances of hex decoders 23 -- instance for 4 LSBs of input 24

sseg_unit_0: entity work.hex_to_sseg

25

port map(hex=>sw(3 downto 0), dp =>’1’,

26

sseg=>led0);

VHDL – continued

27 -- instance for 4 MSBs of input 28

sseg_unit_1: entity work.hex_to_sseg

29

port map(hex=>sw(7 downto 4), dp =>’1’,

30

sseg=>led1);

31 -- instance for 4 LSBs of incremented value 32

sseg_unit_2: entity work.hex_to_sseg

33

port map(hex=>inc(3 downto 0), dp =>’0’,

34

sseg=>led2);

35 -- instance for 4 MSBs of incremented value 36

sseg_unit_3: entity work.hex_to_sseg

37

port map(hex=>inc(7 downto 4), dp =>’1’,

38

sseg=>led3);

39 -- instantiate 7-seg LED display -- 40 --time-multiplexing module 41

disp_unit: entity work.disp_mux

42

port map(

43

clk=>clk, reset=>’0’,

44

in0=>led0, in1=>led1,

45

in2=>led2, in3=>led3,

46

an=>an, sseg=>sseg);

47 end arch;

Testing Result

The generate Statement

Allows the programmer to instantiate an “array” of entities/components. Syntax:

1 label: for parameter in range generate 2

concurrent statements

3 end generate label;

The generate parameter may be used to index array-type signals associated with component ports. Example:

1 architecture GEN of REG_BANK is 2

component REG

3

port(D,CLK,RESET : in std_ulogic;

4

Q : out std_ulogic);

5

end component;

6 begin 7

GEN_REG:

8

for I in 0 to 3 generate

9

REGX : REG port map

10

(DIN(I), CLK, RESET, DOUT(I));

11

end generate GEN_REG;

12 end GEN;

VHDL using generate

14 architecture gen of hex_to_sseg_test is 15

signal inc:std_logic_vector(7 downto 0);

16

signal alldisp:std_logic_vector(15 downto 0);

17

signal led3, led2, led1, led0:

18

std_logic_vector(7 downto 0);

19

signal allled:std_logic_vector(31 downto 0);

20 begin 21 -- increment input (type conversion!) 22

inc <= std_logic_vector(unsigned(sw) + 1);

23 24

• - generate four instances of hex decoders

25

alldisp <= sw & inc; -- combine all hex data to make generate easier

26

allled <= led3 & led2 & led1 & led0; -- combine led lines

27

for i in 0 to 3 generate

28

DECX : entity work.hex_to_sseg_test

29

port map(hex=>alldisp(((i*4)+3) downto (i*4) ), dp =>’1’,

30

sseg=>allled((i*8)+7 downto (1*8)));

31

end generate DECX;

32 33 -- instantiate 7-seg LED display -- 34 --time-multiplexing module 35

disp_unit: entity work.disp_mux

36

port map(

37

clk=>clk, reset=>’0’,

38

in0=>allled(7 downto 0), in1=>alled(15 downto 8),

39

in2=>allled(23 downto 16), in3=>alled(31 downto 24),

40

an=>an, sseg=>sseg);

41 end arch;