CSE141: Introduction to Computer Architecture Hung-Wei Tseng - - PowerPoint PPT Presentation

CSE141: Introduction to Computer Architecture

Hung-Wei Tseng

• What’s your name?
• What’s the most exciting thing you did so far this summer?
• What’s the most interesting computer science topic for you?

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CSE141: Let’s say something!

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We want faster and faster computers!

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What is “architecture”

• "Architecture." Merriam-Webster.com. Merriam-Webster, n.d. Dec 18 2018. <http://www.merriam-webster.com/dictionary/architecture>.

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Computer architecture? Architecture

the art or science of building computers

• What are inside computers?
• Von Neumann architecture
• Current state of CPU architectures
• Why is CSE141 important?
• What’s in this class?

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Outline

What are inside Computers

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CPU+DR AM

CPU DRAM CPU DRAM

CPU

DRAM DRAM DRAM

CPU

DRAM

CPU+DR AM

CPU CPU CPU CPU DRAM DRAM DRAM DRAM

Modern computers

The same spirit, but different implementations

Desktop PC

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PCIe

Memory CPU Socket

SATA

PCI

I/O connectors

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Server

CPU Socket

PCIe

Memory Memory Memory Memory CPU Socket CPU Socket CPU Socket

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Macbook Pro w/ Retina

System Hub Memory CPU Connectors SSD Slot

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iPhone

Sim Card CPU + DRAM

Peripherals Peripherals

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PS4

CPU+ GPU Memory Memory

Memory

Connectors

Peripherals

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Processor/memory is everywhere!

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Processors/CPUs for computers

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Memory/storage for computers

The computer is now like a small network

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SATA SSD HDD Wireless NIC NIC

Processor

DRAM processor-memory bus GPU Accelerator NVMe SSD FPGA/ASIC

In the beginning …

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Difference engine

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1822: English mathematician Charles Babbage conceives of a steam-driven calculating machine that would be able to compute tables of numbers.

ENIAC

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ENIAC(Electronic Numerical Integrator And Computer) was the first electronic general-purpose computer. It was Turing-complete, digital, and could solve "a large class of numerical problems" through reprogramming.

You have to change the physical hardware configuration

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https://az-eandt-live-legacy.azureedge.net/news/2013/apr/images/640_edsac-web.jpg

Von Neumann Architecture & modern computers

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Von Neumann architecture

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memory

2 8 3

CPU is a dominant factor of performance since we heavily rely

• n it to execute programs

By pointing “PC” to different part

• f your memory, we can perform

different functions!

Memory

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You can only store 0 or 1 in each memory cell

• Assume that we have 4 bits


• Example binary arithmetic

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Representing a positive number

Decimal Binary Decimal Binary 0000 4 0100 1 0001 5 0101 2 0010 6 0110 3 0011 7 0111

3 + 2 = 5 0 0 1 1 + 0 0 1 0 1 1 carry 1 3 + 3 = 6 0 0 1 1 + 0 0 1 1 1 1 1 1

• Guidelines
• Obvious representation of 0, 1, 2, ......
• Efficient usage of number space
• Equal coverage of positive and negative numbers
• Easy hardware design
• 1‘s complement + 1 = 2’s complement
• Invert every bit, then + 1
• 1 = b‘1110 + b’1 = b‘1111

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2’s complement

Decimal Binary Decimal Binary 0000

• 1

1111 1 0001

• 2

1110 2 0010

• 3

1101 3 0011

• 4

1100 4 0100

• 5

1011 5 0101

• 6

1010 6 0110

• 7

1001 7 0111

• 8

1000

Does not waste 1111 anymore

• Do we need a separate procedure/hardware for adding positive and negative

numbers?

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Evaluating 2’s complement

• 3 + 2 = 5

• 3 + (-2) = 1

• A. No. The same procedure applies
• B. No. The same “procedure” applies but it changes overflow detection
• C. Yes, and we need a new procedure
• D. Yes, and we need a new procedure and a new hardware
• E. None of the above


0 0 1 1 + 0 0 1 0 1 1 1 0 0 1 1 + 1 1 1 0 1 = 1 1 1 1

Full ALU

30 sign bit (adder output from bit 31) Binvert

CI

Operation

ADD 2 SUB 1 1 2 AND OR 1 SLT 3

• S: sign bit
• Actual Exponent: E - 127
• Mantissa
• Normalized binary significand
• Hidden integer bit: 1
• The actual mantissa is 1.M

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IEEE 754 standard floating point

S E (8 bits) M (23 bits)

• 0 01111110 10000000000000000000000

b‘01111110=126
 126 - 127 = -1 b‘1.1 = 1+1*2-1 = 1.5

1.5 * 2-1 = 0.75

FP add hardware

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Encoding an R-format instruction

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add $v0, $a1, $a2

• pcode

rs rt rd shift amount function

R-format

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

• pcode

rs rt rd shift amount function

00110 000000 100000 00000 00010 00101

Dive into the circuit a bit

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Processor PC

$0 $at $v0 $ra

........

registers ALU

Register file 4-bit ALU memory each of them has different structure — different timing

Register file 4-bit ALU

• A hardware signal defines when data for any specific component is ready to

use by others

• Think about the clock in real life!
• We use edge-triggered clocking
• Values stored in the sequential logic is updated only on a clock edge

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Clock — synchronizing hardware components

clock cycle

memory

Don’t worry — We are not going to talk about the previous 10 slides in detail

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• Instruction fetch: where?

• Decode:
• What’s the instruction?
• Where are the operands?
• Execute
• Memory access
• Where is my data?
• Write back
• Where to put the result
• Determine the next PC

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How CPU handle instructions

Processor PC

120007a30: 0f00bb27 ldah gp,15(t12) 120007a34: 509cbd23 lda gp,-25520(gp) 120007a38: 00005d24 ldah t1,0(gp) 120007a3c: 0000bd24 ldah t4,0(gp) 120007a40: 2ca422a0 ldl t0,-23508(t1) 120007a44: 130020e4 beq t0,120007a94 120007a48: 00003d24 ldah t0,0(gp) 120007a4c: 2ca4e2b3 stl zero,-23508(t1)

instruction memory data memory

800bf9000: 00c2e800 12773376 800bf9004: 00000008 8
 800bf9008: 00c2f000 12775424
 800bf900c: 00000008 8 800bf9010: 00c2f800 12777472
 800bf9014: 00000008 8
 800bf9018: 00c30000 12779520
 800bf901c: 00000008 8

$0 $at $v0 $ra

........

registers ALU

program counter & instruction memory registers ALUs data memory registers

Current state of CPU architectures

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Moore’s Law

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• The number of transistors we can build in a fixed area of silicon doubles

every 12 ~ 24 months.

(1) Moore, G. E. (1965), 'Cramming more components onto integrated circuits', Electronics 38 (8) . (1) Transistor Count 1 10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000 10,000,000,000 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015

Moore’s Law is the most important driver for historic CPU performance gains

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CPU performance scales well before 2002

• 52%/year

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The slowdown of CPU scaling

SPECRate 10 20 30 40 50 60 70 80 90 Sep-06 Dec-06 Mar-07 Jun-07 Sep-07 Dec-07 Mar-08 Jun-08 Sep-08 Dec-08 Mar-09 Jun-09 Sep-09 Dec-09 Mar-10 Jun-10 Sep-10 Dec-10 Mar-11 Jun-11 Sep-11 Dec-11 Mar-12 Jun-12 Sep-12 Dec-12 Mar-13 Jun-13 Sep-13 Dec-13 Mar-14 Jun-14 Sep-14 Dec-14 Mar-15 Jun-15 Sep-15 Dec-15 Mar-16 Jun-16 Sep-16 Dec-16 Mar-17 Jun-17 Sep-17

5x in 67 months 1.5x in 67 months

Power limits CPU performance scaling

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istor Performance vs. Leakage

1x 0.001x 0.01x 0.1x 14 nm 22 nm 32 nm 45 nm 65 nm

Lower Leakage Power Higher Transistor Performance (switching speed)

Static power under different process technologies

• Power = Active Power + Leakage Power
• Active Power =aCV2f
• a: switches per cycle
• C: capacitance
• V: voltage
• f: frequency, usually 


linear with V

• Static power
• Roughly a fixed 


percentage of active power

• Increasing as frequency goes higher
• To limit static power, you cannot lower your Vdd and Vt

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Leakage power becomes increasingly significant

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• Multi-processors
• Two must be faster than one!
• “Theoretically,” they double the performance without changing the clock speed.
• Seems simple, but...
• Speeding up a single CPU makes everything faster!
• An application’s performance double every 18 months with no effort on the programmer’s part.
• Getting performance out of a multiprocessor is difficult.
• Parallelizing code is difficult, it takes (lots of) work
• There aren’t that many threads. Threads incur overhead, too.
• Remember or look forward to CSE141

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The rise of parallelism

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Intel P4 (2000) 1 core Intel Nahalem (2010) 4 cores Nvidia Tegra 3 (2011) 5 cores SPARC T3 (2010) 16 cores AMD Zambezi (2011) 16 cores AMD Athlon 64 X2 
 (2005) 2 cores

Computers become heterogeneous

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GPU TPU CPU DRAM SSD H.D.D. Network Interface FPGA

Additional data movement

Why this course & what’s in this class

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Connecting to the physical world…

Physics/Materials Devices Micro-architecture Instruction Set Architectures Processors

Why this course?

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JVM

Instruction Set 
 Architecture Operating
 Systems Compilers
 Runtime
 Virtual Machines Programming
 Languages Programmers/
 Users

• Understand how CPUs/GPUs run programs
• Understand why CPU/system performance (and other metrics) varies
• Understand why program performance varies
• Understand how to write efficient programs!

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Why this course?

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Live demo!

if(option) std::sort(data, data + arraySize); for (unsigned c = 0; c < arraySize*10000; ++c) { if (data[c%arraySize] >= rand()) sum ++; } }

if option is set to 1 —> O(nlogn),

• therwise, O(n)

• Instruction set architectures
• MIPS
• ISAs and the compiler
• Measuring performance
• Amdahl’s Law
• Performance measurement
• Metrics
• Processor design
• Basic design
• Pipelining
• Dealing with hazards
• Speculation and control
• Improving ILP
• The memory system
• Memory technologies
• Caching
• Introduction to multiprocessors —

pthread programming

• GPU architecture

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What’s in the class

Date Topic Readings Due 2019/08/05 (8a) Introduction & ISA 2019/08/05 (9:30a) ISA 2.1-2.7, 2.10, 2.8, 2.12, 2.13, 2.14 and 2.17 2019/08/07 (8a) Performance Evaluation 1.5-1.10 Reading quizzes for 1.5-1.10 due before class 2019/08/07 (9:30a) Performance Evaluation (II) 2019/08/12 (8a) Performance (III) and Single-cycle Processor Design 4.1-4.4 Homework 1 due before class Reading quizzes for 4.1-4.9 due before class 2019/08/12 (9:30a) Pipeline processor 4.5-4.9 2019/08/14 (8a) Pipeline Processor (II) Reading quizzes for 4.5-4.9 due before class 2019/08/14 (9:30a) Pipeline (III) 2019/08/19 (8a) Branch Prediction Homework 2 due before class Reading quizzes for 5.1-5.4 due before class 2019/08/19 (9:30a) Midterm Review 2019/08/21(8a) Midterm 2019/08/21 (9:30a) Memory and caching 5.1-5.4 2019/08/26 (8a) Memory and caching 5.1-5.4 Homework 3 due Reading quizzes for 5.1-5.4 due before class 2019/08/26 (9:30a) Memory and caching 5.8 2019/08/28 (8a) Memory and caching Reading quizzes for 5.6 and 5.7 due before class 2019/08/28 (9:30a) Virtual Memory 5.6 and 5.7 2019/09/04(8a) Modern Processor Design 4.10 Homework 4 due before class
 Reading quizzes for 6.4-6.5, 5.10 due before class 2019/09/04(9:30a) Introduction to multithreaded processors 6.4-6.5 2019/09/04 (2p) Final Review 2019/9/7 Final

Tentative Schedule

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You need to complete the reading of H&P Check due dates here Subject to change

Logistics

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• Lectures: MW 8a-9:20a, 9:30a-10:50a, PCH 120
• Course webpage:


http://cseweb.ucsd.edu/classes/su19_2/cse141-a/

• Discussion on piazza


https://piazza.com/class/jyvn9cs1nxx4m5

• We do podcasting


https://podcast.ucsd.edu/watch/s219/cse141_a00
 


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Course resource

• Hung-Wei Tseng
• https://intra.engr.ucr.edu/~htseng/
• Office hour: MW 1:30p-2:30p @ EBU3B 3236
• E-mail: htseng+CSE141@eng.ucsd.edu

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Instructor

• Harish Prasanth
• Office hours: TuTh 12p-1p @ EBU3B B260A
• E-mail: hgajendr@eng.ucsd.edu

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Teaching Assistant

• Login/discussion in TritonEd and piazza.
• Read the text before class!
• Computer Organization and Design: The Hardware/Software Interface (5th Edition) --

previous editions are not supported

• I’m not going to cover everything in class, but you are responsible for all the assigned

text.

• Reading quizzes in TritonEd (15%)
• Come to class (10%)
• I will cover things not in the book.
• 10% from clickers
• Homework throughout the course. (15%)
• Help to practice the concepts from each topic
• Midterm (25%)
• Cumulative final (35%)

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Your tasks

• Questions about the assigned reading on
• Complete before class begins
• There is one due Wednesday!
• Be sure to check the website for the reading quizzes!

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Reading quizzes

Most lectures today …

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Me

Me You

I expect the lecture to be…

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• I’ll bring in activities to ENGAGE you in exploring your understanding of the

material

• Let you practice
• Bring out misconceptions
• Let us LEARN from each other about difficult parts.
• You will be GET CREDIT for your efforts to learn in class
• By answering questions with a clicker (iClicker)
• Answer 80% of the clicker questions in class, get 9% of your final grade
• Process: Individual Think/Answer, Group Discussion, Group Answer

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Peer instruction

CSE 141 - Intro/Computer Architecture - Tseng [S119] (Course is unavailable to students) Tools

Tools

Announcements Create and view Course Announcements. Blogs Create and manage blogs for Courses and Course Groups. Calendar Track important events and dates through the Calendar. Contacts Instructors can post contact information about themselves and others. Discussion Board Create and manage Forums within the Discussion Board. Glossary View a list of important terms and their denitions. Groups Create and manage formal groups of students to collaborate on work. Journals Create and manage journals that can be assigned to each user in a group for the purposes of private communication with the instructor. My Grades Displays detailed information about your grades. Tasks Use tasks to keep track of work that must be completed. Each Task has a status and a due date. Wikis Create and manage wikis for Courses and Course Groups WileyPLUS Open the complete eTextbook for your course. Start using WileyPLUS for your assignments. Zoom Meeting i>clicker Student Registration Register your i>clicker Remote ID

?

Student Preview mode is ON

Exit Preview Settings

• Set your channel to “CA”
• Register your i-clicker
• You can do this through TritonEd

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Setup your i-clicker

• Assigned on Wednesdays, due on Mondays, before the lecture
• The best way to prepare the examines
• Submit through TritonEd.

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Assignments

• You can see your grades on TritonEd.


• Errors in grading
• If you feel there has been an error in how an assignment or test was graded, you have one week

from when the assignment is return to bring it to our attention. You must submit (via email to the instructor and the appropriate TAs) a written description of the problem. Neither I nor the TAs will discuss regrades without receiving an email from you about it first.

• For arithmetic errors (adding up points etc.)
• you do not need to submit anything in writing, but the one week limit still applies.

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Grading

• Don’t cheat.
• Cheating on a test will get you an F in the class and no option to drop, and a visit with your

college dean.

• Cheating on homework means you don’t have to turn them in any more, but you don’t get

points either. You will also take at least 25% penalty on the exam grades.

• Copying solutions of the internet or a solutions manual is cheating
• They are incorrect sometimes
• Review the UCSD student handbook
• When in doubt, ask.

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Academic Honesty

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You