CENG 342 Digital Systems LPU Computer Larry Pyeatt SDSM&T - PowerPoint PPT Presentation

CENG 342 – Digital Systems LPU Computer Larry Pyeatt SDSM&T

LPU Computer BRclk Memory buttons[4:0] BRclk RXD RXD clkgen address[15:0] TXD clock TXD clk_in1 buttons[4:0] data_out[15:0] clk_reset_i irst_reg I0 O clk100_ce cpuclk CLR byte leds[15:0] reset leds[15:0] cpuclk_ce locked C clk ready RTL_INV memclk_ce memclk CE Q data_in[15:0] rgb_leds[5:0] rgb_leds[5:0] clken_i D I0 reset en sseg[7:0] sseg[7:0] O I1 clk_wiz_0 RTL_REG_ASYNC rd sseg_an[7:0] sseg_an[7:0] RTL_AND reset switches[15:0] wr irst1_i CPU Memory I0 irst0_i O I0 = I1 O MAddr[15:0] I1 RTL_EQ MDatai[15:0] MDatao[15:0] RTL_AND Mready Mbyte clock Menable switches[15:0] reset Mread Mwrite CPU

Memory Memory RAM[3].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 3 ena wea[1:0] blk_mem_gen_0 RAM[4].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 4 ena wea[1:0] blk_mem_gen_0 RAM[5].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 5 ena wea[1:0] blk_mem_gen_0 RAM[6].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 6 ena wea[1:0] blk_mem_gen_0 RAM[7].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 7 ena wea[1:0] blk_mem_gen_0 RAM[8].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 8 ena wea[1:0] blk_mem_gen_0 RAM[9].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 9 ena wea[1:0] blk_mem_gen_0 ROM1 address[11:0] data[15:0] 0 en ROM RAM[10].RAM_i bank_do_i[15]_i addra[11:0] I0[15:0] clka S=4'b1111 S=4'b1110 I1[15:0] dina[15:0] douta[15:0] S=4'b0101 I10[15:0] 10 ena wea[1:0] S=4'b0100 I11[15:0] S=4'b0011 I12[15:0] blk_mem_gen_0 I13[15:0] S=4'b0010 RAM[11].RAM_i S=4'b0001 I14[15:0] S=4'b0000 I15[15:0] O[15:0] addra[11:0] S=4'b1101 I2[15:0] clka S=4'b1100 I3[15:0] dina[15:0] douta[15:0] S=4'b1011 I4[15:0] 11 ena S=4'b1010 I5[15:0] wea[1:0] I6[15:0] S=4'b1001 blk_mem_gen_0 S=4'b1000 I7[15:0] S=4'b0111 I8[15:0] RAM[12].RAM_i S=4'b0110 I9[15:0] RTL_MUX addra[11:0] S[3:0] clka ... dina[15:0] douta[15:0] 12 ena wea[1:0] blk_mem_gen_0 RAM[13].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 13 ena wea[1:0] blk_mem_gen_0 RAM[14].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 14 ena wea[1:0] blk_mem_gen_0 RAM[15].RAM_i addra[11:0] clka dina[15:0] douta[15:0] 15 ena wea[1:0] blk_mem_gen_0 ROM2 address[11:0] data[15:0] 1 en ROM__parameterized0 BRclk RXD IO address[15:0] buttons[4:0] BRclk byte RXD clka0_i ... addr[11:0] TXD TXD clk I0 O buttons[4:0] dout[15:0] RTL_INV ctrl clk leds[15:0] din[15:0] rgb_leds[5:0] en sseg[7:0] addr[15:0] bank_addr[11:0] 2 bank_do[15:0] bank_di[15:0] rst sseg_an[7:0] switches[15:0] byte bank_di_i bank_ena[15:0] clk I0[15:0] bank_wea[1:0] we[1:0] ... S=1'b1 O[15:0] IO data_out[15:0] data_in[15:0] data_in[15:0] S=default I1[15:0] data_out[15:0] leds[15:0] en en ready S RTL_MUX ready rd rd rgb_leds[5:0] reset reset wr sseg[7:0] sseg_an[7:0] memory_controller switches[15:0] wr Memory

I/O Memory IO UART_din_i 7:0 S=1'b0 I0[7:0] O[7:0] ... S=default I1[7:0] UART_dev RTL_MUX S 0 2:0 ADD[2:0] BRclk BR_clk CS CTSn dev_do[5]_i D[7:0] I0[15:0] 7:0 S=1'b0 O[15:0] DCDn RD[7:0] ... S=default I1[15:0] DSRn sTX TXD RTL_MUX S RIn 0 WR rst0_i I0 O clk RXD dout_i RTL_INV rst I0[15:0] sRX S=1'b0 O[15:0] S=default I1[15:0] CS0_i gh_uart_16550 5 I0 O S RTL_MUX dout_i__1 RTL_INV 5 S=1'b0 I0[15:0] O[15:0] dout[15:0] dout_i__0 I1[15:0] S=default buton_dev S=1'b0 I0[15:0] addr[11:0] RTL_MUX O[15:0] S S=default I1[15:0] buttons[4:0] buttons[4:0] data_out[15:0] 3 RTL_MUX 4 en S rgb_led_dev buttons 4 clk clock din[15:0] data_in[15:0] leds[5:0] en en0_i 2 en I0 O reset RTL_INV rgb_leds io_decoder UART_wr_i rst WR0_i UART_wr2_i S=1'b1 I0 en Y[255:0] I0 O I0 O led_dev 5 O S=default I1 sel[7:0] I1 = ... RTL_INV RTL_MUX clock ...c_decoder_with_enable__parameterized1 RTL_EQ S I0 UART_wr1_i data_in[15:0] switch_dev O I1 en leds[15:0] leds[15:0] 1 UART_wr2_i__0 RTL_AND 3 en data_out[15:0] reset rgb_leds[5:0] I0 0 O switches[15:0] we[1:0] I1 1 switches leds RTL_OR switches[15:0] hex_dev we[1:0] address[2:0] 2:1 clock data_in[15:0] sseg[7:0] sseg[7:0] 0 en sseg_an[7:0] sseg_an[7:0] reset we[1:0] hexdisplay IO Memory

LPU Computer BRclk Memory buttons[4:0] BRclk RXD RXD clkgen address[15:0] TXD clock TXD clk_in1 buttons[4:0] data_out[15:0] clk_reset_i irst_reg I0 O clk100_ce cpuclk CLR byte leds[15:0] reset leds[15:0] cpuclk_ce locked C clk ready RTL_INV memclk_ce memclk CE Q data_in[15:0] rgb_leds[5:0] rgb_leds[5:0] clken_i D I0 reset en sseg[7:0] sseg[7:0] O I1 clk_wiz_0 RTL_REG_ASYNC rd sseg_an[7:0] sseg_an[7:0] RTL_AND reset switches[15:0] wr irst1_i CPU Memory I0 irst0_i O I0 = I1 O MAddr[15:0] I1 RTL_EQ MDatai[15:0] MDatao[15:0] RTL_AND Mready Mbyte clock Menable switches[15:0] reset Mread Mwrite CPU

LPU CPU CPU ID SQ DP ALUfunc[3:0] clk Asel[2:0] cwin[0:16] ALUfunc[3:0] I[15:0] Bsel[2:0] ready cwout[0:16] Memin[15:0] flags[0:3] Dsel[2:0] rst asel[2:0] T[3:0] t[3:0] bsel[2:0] Addr[15:0] MAddr[15:0] control[0:16] clk Memout[15:0] MDatao[15:0] sequencer imm[15:0] cw[0:16] flags[0:3] dsel[2:0] instruction_decoder imm[15:0] MDatai[15:0] rst Mbyte 11 Mready Menable data_path 10 clock Mread 12 Mwrite 13 IR clk d[15:0] q[15:0] 0 en reset reset generic_register CPU

LPU Sequencer Sequencer is a finite state machine. Inputs: Control word from Instruction Decoder Instruction type from Instruction Decoder Ready signal from Memory CPU clock Reset Outputs: Final control word Control signals to Datapath Control signals to Memory Control signal to latch the Instruction Register Control signal to disable the CPU clock

LPU Sequencer State Diagram reset=0 Reset reset=0 reset=1 reset=0 Itype!=Load/Store or Ready=1 Fetch1 Ex1 Ready=1 MARsel=0 MARsel=0 MARle=0 MARle=0 reset=0 PCie=0 reset=0 Sequencer Passes Sequencer Provides Control Control Word From Words to Load Next Instruction ID to Datapath, But Into the IR, Using the PC May Override For Ready=0 Itype=Load/Store and Ready=0 to Provide the Address Load/Store Instructions Ready=1 Ready=1 Fetch2 Ex2 MARsel=1 MARsel=1 MARle=1 MARle=1 Ready=0 Ready=0 Some control signals may not be shown. You may need to make additions and/or corrections.

LPU Datapath Data_out PCAsel IMM IMMBsel ALUfunc CCRle MARle MARsel B bus Asel Bsel A bus Dsel Dlen ALU Register File DIsel CCR Data_in PC MAR D bus Address PCle PCie PCDsel Flags