CENG 342 Digital Systems LPU Computer Larry Pyeatt SDSM&T - - PowerPoint PPT Presentation

▶

Aug 31, 2023 148 likes •245 views

CENG 342 Digital Systems LPU Computer Larry Pyeatt SDSM&T LPU Computer BRclk Memory buttons[4:0] BRclk RXD RXD clkgen address[15:0] TXD clock TXD clk_in1 buttons[4:0] data_out[15:0] clk_reset_i irst_reg I0 O clk100_ce

SLIDE 1

CENG 342 – Digital Systems

LPU Computer Larry Pyeatt

SDSM&T

SLIDE 2

LPU Computer

buttons[4:0] RXD clock reset switches[15:0] clk_reset_i RTL_INV I0 O clken_i RTL_AND I0 I1 O = irst1_i RTL_EQ I0 I1 O clkgen clk_wiz_0 clk100_ce clk_in1 cpuclk cpuclk_ce locked memclk memclk_ce reset irst0_i RTL_AND I0 I1 O irst_reg RTL_REG_ASYNC C CE CLR D Q CPU CPU Mbyte Menable Mread Mready Mwrite clock reset MAddr[15:0] MDatai[15:0] MDatao[15:0] Memory Memory BRclk RXD TXD byte clk en rd ready reset wr address[15:0] buttons[4:0] data_in[15:0] data_out[15:0] leds[15:0] rgb_leds[5:0] sseg[7:0] sseg_an[7:0] switches[15:0] TXD leds[15:0] rgb_leds[5:0] sseg[7:0] sseg_an[7:0] BRclk

SLIDE 3

Memory

Memory Memory BRclk RXD TXD byte clk en rd ready reset wr address[15:0] buttons[4:0] data_in[15:0] data_out[15:0] leds[15:0] rgb_leds[5:0] sseg[7:0] sseg_an[7:0] switches[15:0] ctrl memory_controller byte clk en rd ready reset wr addr[15:0] bank_addr[11:0] bank_di[15:0] bank_do[15:0] bank_ena[15:0] bank_wea[1:0] data_in[15:0] data_out[15:0] RAM[3].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[4].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[5].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[6].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[7].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[8].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[9].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[10].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[11].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[12].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[13].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[14].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] RAM[15].RAM_i blk_mem_gen_0 clka ena addra[11:0] dina[15:0] douta[15:0] wea[1:0] ROM1 ROM en address[11:0] data[15:0] ROM2 ROM__parameterized0 en address[11:0] data[15:0] bank_do_i[15]_i RTL_MUX I0[15:0] S=4'b1111 I1[15:0] S=4'b1110 I10[15:0] S=4'b0101 I11[15:0] S=4'b0100 I12[15:0] S=4'b0011 I13[15:0] S=4'b0010 I14[15:0] S=4'b0001 I15[15:0] S=4'b0000 I2[15:0] S=4'b1101 I3[15:0] S=4'b1100 I4[15:0] S=4'b1011 I5[15:0] S=4'b1010 I6[15:0] S=4'b1001 I7[15:0] S=4'b1000 I8[15:0] S=4'b0111 I9[15:0] S=4'b0110 O[15:0] S[3:0] clka0_i RTL_INV I0 O IO IO BRclk RXD TXD clk en rst addr[11:0] buttons[4:0] din[15:0] dout[15:0] leds[15:0] rgb_leds[5:0] sseg[7:0] sseg_an[7:0] switches[15:0] we[1:0] bank_di_i RTL_MUX S I0[15:0] S=1'b1 I1[15:0] S=default O[15:0] ... ... 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 ...

SLIDE 4

I/O

Memory Memory IO IO BRclk RXD TXD clk en rst addr[11:0] buttons[4:0] din[15:0] dout[15:0] leds[15:0] rgb_leds[5:0] sseg[7:0] sseg_an[7:0] switches[15:0] we[1:0] CS0_i RTL_INV I0 O UART_dev gh_uart_16550 BR_clk CS CTSn DCDn DSRn RIn WR clk rst sRX sTX ADD[2:0] D[7:0] RD[7:0] UART_din_i RTL_MUX S I0[7:0]

S=1'b0 I1[7:0] S=default O[7:0]

UART_wr_i RTL_MUX I0

S=1'b1 I1 S=default O S

UART_wr1_i RTL_AND I0 I1 O = UART_wr2_i RTL_EQ I0 I1 O UART_wr2_i__0 RTL_OR I0 I1 O WR0_i RTL_INV I0 O buton_dev buttons en buttons[4:0] data_out[15:0] dev_do[5]_i RTL_MUX S I0[15:0]

S=1'b0 I1[15:0] S=default O[15:0]

dout_i RTL_MUX S I0[15:0]

S=1'b0 I1[15:0] S=default O[15:0]

dout_i__0 RTL_MUX S I0[15:0]

S=1'b0 I1[15:0] S=default O[15:0]

dout_i__1 RTL_MUX S I0[15:0]

S=1'b0 I1[15:0] S=default O[15:0]

en0_i RTL_INV I0 O hex_dev hexdisplay clock en reset address[2:0] data_in[15:0] sseg[7:0] sseg_an[7:0] we[1:0] io_decoder ...c_decoder_with_enable__parameterized1 en Y[255:0] sel[7:0] led_dev leds clock en reset data_in[15:0] leds[15:0] we[1:0] rgb_led_dev rgb_leds clock en reset data_in[15:0] leds[5:0] rst0_i RTL_INV I0 O switch_dev switches en data_out[15:0] switches[15:0]

... 7:0 ... 2:1 2:0 5 5 4 4 5 3 3 2 1 7:0 ... 1

SLIDE 5

LPU Computer

SLIDE 6

LPU CPU

CPU CPU Mbyte Menable Mread Mready Mwrite clock reset MAddr[15:0] MDatai[15:0] MDatao[15:0] DP data_path clk rst ALUfunc[3:0] Addr[15:0] Memin[15:0] Memout[15:0] asel[2:0] bsel[2:0] cw[0:16] dsel[2:0] flags[0:3] imm[15:0] ID instruction_decoder ALUfunc[3:0] Asel[2:0] Bsel[2:0] Dsel[2:0] I[15:0] T[3:0] control[0:16] flags[0:3] imm[15:0] IR generic_register clk en reset d[15:0] q[15:0] SQ sequencer clk ready rst cwin[0:16] cwout[0:16] t[3:0]

11 10 12 13

SLIDE 7

LPU Sequencer

Sequencer is a finite state machine. Inputs:

Control word from Instruction Decoder Instruction type from Instruction Decoder Ready signal from Memory CPU clock Reset

Outputs: Final control word

Control signals to Datapath Control signals to Memory Control signal to latch the Instruction Register Control signal to disable the CPU clock

SLIDE 8

LPU Sequencer State Diagram

Reset

ID to Datapath, But Sequencer Passes May Override For Load/Store Instructions Control Word From Words to Load Next Instruction Sequencer Provides Control Into the IR, Using the PC to Provide the Address Ready=0 MARsel=1 reset=1 Ready=1 Ready=0 reset=0 MARle=1

Fetch2 Ex2 Ex1

reset=0

Fetch1

Ready=1 reset=0 reset=0 reset=0 Itype!=Load/Store or Ready=1 Ready=0 Itype=Load/Store and Ready=0 Ready=1 PCie=0 MARsel=0 MARle=0 MARsel=0 MARsel=1 MARle=1 MARle=0

Some control signals may not be shown. You may need to make additions and/or corrections.

SLIDE 9

LPU Datapath

Register File ALU PC CCR MAR PCle PCie PCDsel CCRle Flags MARle MARsel ALUfunc IMMBsel Data_in DIsel Dlen Dsel Bsel Asel Address Data_out PCAsel IMM A bus B bus D bus