CENG 342 Digital Systems Register-Transfer (RT) Level Combinational - PowerPoint PPT Presentation

CENG 342 – Digital Systems Register-Transfer (RT) Level Combinational Circuit Larry Pyeatt SDSM&T

RT-Level Description Gate-level Design RT-level Design (module-level) Adders Comparators Decoders Multiplexers VHDL operators and routing constructs RT-level combinational circuits

Operators - arithmetic, structural, relational, and logical Operator Description Data type of operands Data type of Result a ** b exponentiation integer integer a * b multiplication integer integer a / b division integer integer a + b addition integer integer subtraction integer integer a - b a & b concatenation 1-D array, element 1-D array equal to any boolean a = b not equal to any boolean a /= b less than scalar or 1-D array boolean a < b less than or equal to scalar or 1-D array boolean a <= b greater than scalar or 1-D array boolean a > b a >= b greater than or equal to scalar or 1-D array boolean negation scalar or 1-D array same as operand not a and boolean, std_logic , std_logic_vector same as operands a and b or boolean, std_logic , std_logic_vector same as operands a or b exclusive or boolean, std_logic , std_logic_vector same as operands a xor b

Operators and data types in IEEE numeric_std package The IEEE numeric_std package is part of the IEEE library. It: adds two data types: unsigned , and signed , and defines the relational and arithmetic operations over those data types. To use the package, add to the top of your VHDL file: 1 library ieee; 2 use ieee.numeric_std.all -- include numeric_std package Operator Description Data type of operands Data type of Result multiplication unsigned, natural, signed, integer unsigned, signed a * b addition unsigned, natural, signed, integer unsigned, signed a + b subtraction unsigned, natural, signed, integer unsigned, signed a - b a = b equal to unsigned, natural, signed, integer boolean a /= b not equal to unsigned, natural, signed, integer boolean a < b less than unsigned, natural, signed, integer boolean a <= b less than or equal to unsigned, natural, signed, integer boolean a > b greater than unsigned, natural, signed, integer boolean a >= b greater than or equal to unsigned, natural, signed, integer boolean

Type hierarchy Type Value Package true, false VHDL standard boolean − ( 2 31 ) to ( 2 31 − 1 ) integer VHDL standard natural zero and positive integers VHDL standard ’U’ , ’X’ , ’0’ , ’1’ , ’Z’ , ’W’ , ’L’ , ’H’ , ’-’ std_logic std_logic_1164 array of std_logic std_logic_vector std_logic_1164 array of std_logic unsigned numeric_std array of std_logic signed numeric_std Example: signal A_unsigned : unsigned(3 downto 0) ; 1 signal B_signed : signed (3 downto 0) ; 2 signal C_slv : std_logic_vector (3 downto 0) ; 3 . . . 4 A_unsigned <= "1111" ; -- set A_unsigned to 15 5 B_signed <= "1111" ; -- set B_signed to -8 6 C_slv <= "1111" ; -- set C_slv to "1111" 7

Example signal A, B, Result : unsigned(7 downto 0) ; 1 signal Result1 : unsigned(8 downto 0) ; 2 signal Result2 : unsigned(6 downto 0) ; 3 . . . 4 -- simple addition, no carry out 5 Result <= A + B ; 6 -- with carry out ? 7 Result1 <= (’0’ & A) + (’0’ & B) 8 -- For a smaller result, take slices of input arrays 9 Result2 <= A(6 downto 0) + B(6 downto 0) ; 10 Length of result depends on length of operands and the operation being performed. 1 Y <= A; -- Y’Length = A’Length 2 Y <= A and B; -- Y’Length = A’Length = B’Length 3 W <= A > B; -- Boolean: W is one bit 4 Y <= A + B; -- Y’Length = Maximum(A’Length, B’Length) or +1 with carry out 5 V <= A * B; -- Y’Length = A’Length + B’Length

Type Conversions The std_logic_vector , unsigned , and signed types are defined as arrays with elements of std_logic . They are not the same type as the built-in boolean , integer , and natural , types, but sometimes it is necessary to work with combinations of these types. There are conversion (typecasting) functions. Data type of a To data type Conversion function unsigned or signed std_logic_vector std_logic_vector(a) signed or std_logic_vector unsigned unsigned(a) unsigned or std_logic_vector signed signed(a) unsigned or signed integer to_integer(a) natural unsigned to_unsigned(a, size) integer signed to_signed(a, size) Example: 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); 3 variable i: natural; 4 ... a1 <= std_logic_vector (b1); 5 b3 <= unsigned (a4); 6 b3 <= to_unsigned(i,4); 7 a2 <= std_logic_vector (to_unsigned(3,4)); 8

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? a3 <= a1 + a2 a2 <= a1 + 2 b3 <= b1 + b2 b2 <= b1 + 2 a3 <= a1 * a2 b3 <= b1 * b2

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? N a3 <= a1 + a2 a2 <= a1 + 2 b3 <= b1 + b2 b2 <= b1 + 2 a3 <= a1 * a2 b3 <= b1 * b2

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? N a3 <= a1 + a2 a2 <= a1 + 2 N b3 <= b1 + b2 b2 <= b1 + 2 a3 <= a1 * a2 b3 <= b1 * b2

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? N a3 <= a1 + a2 a2 <= a1 + 2 N Y b3 <= b1 + b2 b2 <= b1 + 2 a3 <= a1 * a2 b3 <= b1 * b2

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? N a3 <= a1 + a2 a2 <= a1 + 2 N Y b3 <= b1 + b2 Y b2 <= b1 + 2 a3 <= a1 * a2 b3 <= b1 * b2

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? N a3 <= a1 + a2 a2 <= a1 + 2 N Y b3 <= b1 + b2 Y b2 <= b1 + 2 a3 <= a1 * a2 N b3 <= b1 * b2

Type Conversions - Quiz 1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); Statement Valid? N a3 <= a1 + a2 a2 <= a1 + 2 N Y b3 <= b1 + b2 Y b2 <= b1 + 2 a3 <= a1 * a2 N Y b3 <= b1 * b2

Other synthesis-related VHDL constructs Concatenation operator: & is used to combine segments of small arrays to form a bigger array. Example1: shifting a signal for a fixed amount signal a: std_logic_vector (6 downto 0); 1 signal shift1, shift2, shift3: std_logic_vector (6 downto 0); 2 ... 3 shift1 <= a(2 downto 0) & a(6 downto 3); -- rotate right 3 bits 4 shift2 <= "000" & a(6 downto 3); -- logical shift right 3 bits 5 Shift3 <= a(6) & a(6) & a(6 downto 2); -- arithmetic shift right 3 bits 6 Example2: addition with carry out signal A, B: unsigned(7 downto 0) ; 1 signal Result1 : unsigned(8 downto 0) ; 2 ... 3 -- addition with carry out 4 Result1 <= (’0’ & A) + (’0’ & B) ; 5

Array aggregation VHDL has some handy syntax for assigning values to arrays. Example: a <= "10100000"; 1 a <= (7=>’1’, 6=>’0’, 0=>’0’, 1=>’0’, 5=>’1’, 4=>’0’, 3=>’0’, 2=>’1’); 2 a <= (7|5=>’1’, 6|4|3|2|1|0=>’0’); 3 a <= (7|5=>’1’, others=>’0’); 4 Note that " is used for multiple bits, and ’ is used for single bits.

Tri-state buffer A logic component that is not always covered in the introductory logic course. It can output ’0’, ’1’ or ’Z’. The ’Z’ output high impedence, or open circuit. In other words, the component is not outputting logic high or low, and it is as if it is not connected at all. The diagram and truth table are: Core of the VHDL code for the tri-state buffer: 1 y <= a_in when oe=’1’ else ’Z’; Example: implement a bidirectional port to better utilize a I/O pin: ... 1 2 bi <= sig_out when dir=’1’ else ’Z’; 3 sig_in <=bi;

Summary A small set of data types and operators are needed in our class for the purpose of synthesis If no arithmetic operations, use std_logic and std_logic_vector for entity port declaration and internal signals. ’Z’ value is only used in a tri-state buffer. For internal signals with arithmetic operations, use the IEEE numeric_std package and its unsigned and signed types Use integer and arithmetic operators for constant and array boundary, but not for a signal’s data type. Use the result of a relational operation (Boolean data type) in routing constructs. Use a user-defined two-directional data type for two-dimensional storage array (Chapter 4) Use a user-defined enumerate data type for the symbolic states of a finite state machine (Chapter 5) Reference: http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf