CENG 342 Digital Systems Register-Transfer (RT) Level Combinational - - PowerPoint PPT Presentation

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Oct 03, 2023 159 likes •345 views

CENG 342 Digital Systems Register-Transfer (RT) Level Combinational Circuit Larry Pyeatt SDSM&T RT-Level Description Gate-level Design RT-level Design (module-level) Adders Comparators Decoders Multiplexers VHDL operators and

SLIDE 1

CENG 342 – Digital Systems

Register-Transfer (RT) Level Combinational Circuit Larry Pyeatt

SDSM&T

SLIDE 2

RT-Level Description

Gate-level Design RT-level Design (module-level)

Adders Comparators Decoders Multiplexers

VHDL operators and routing constructs RT-level combinational circuits

SLIDE 3

Operators - arithmetic, structural, relational, and logical

Operator Description Data type of operands Data type of Result a ** b exponentiation integer integer a * b multiplication integer integer a / b division integer integer a + b addition integer integer a - b subtraction integer integer a & b concatenation 1-D array, element 1-D array a = b equal to any boolean a /= b not equal to any boolean a < b less than scalar or 1-D array boolean a <= b less than or equal to scalar or 1-D array boolean a > b greater than scalar or 1-D array boolean a >= b greater than or equal to scalar or 1-D array boolean not a negation scalar or 1-D array same as operand a and b and boolean, std_logic, std_logic_vector same as operands a or b

boolean, std_logic, std_logic_vector same as operands a xor b exclusive or boolean, std_logic, std_logic_vector same as operands

SLIDE 4

Operators and data types in IEEE numeric_std package

The IEEE numeric_std package is part of the IEEE library. It: adds two data types: unsigned, and signed, and defines the relational and arithmetic operations over those data types. To use the package, add to the top of your VHDL file:

1 library ieee; 2 use ieee.numeric_std.all -- include numeric_std package

Operator Description Data type of operands Data type of Result a * b multiplication unsigned, natural, signed, integer unsigned, signed a + b addition unsigned, natural, signed, integer unsigned, signed a - b subtraction unsigned, natural, signed, integer unsigned, signed a = b equal to unsigned, natural, signed, integer boolean a /= b not equal to unsigned, natural, signed, integer boolean a < b less than unsigned, natural, signed, integer boolean a <= b less than or equal to unsigned, natural, signed, integer boolean a > b greater than unsigned, natural, signed, integer boolean a >= b greater than or equal to unsigned, natural, signed, integer boolean

SLIDE 5

Type hierarchy

Type Value Package boolean true, false VHDL standard integer −(231) to (231 − 1) VHDL standard natural zero and positive integers VHDL standard std_logic ’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’-’ std_logic_1164 std_logic_vector array of std_logic std_logic_1164 unsigned array of std_logic numeric_std signed array of std_logic numeric_std

Example:

signal A_unsigned : unsigned(3 downto 0) ;

signal B_signed : signed (3 downto 0) ;

signal C_slv : std_logic_vector (3 downto 0) ;

. . .

A_unsigned <= "1111" ; -- set A_unsigned to 15

B_signed <= "1111" ;

- set B_signed to -8

C_slv <= "1111" ;

- set C_slv to "1111"

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Example

signal A, B, Result : unsigned(7 downto 0) ;

signal Result1 : unsigned(8 downto 0) ;

signal Result2 : unsigned(6 downto 0) ;

. . .

- simple addition, no carry out

Result <= A + B ;

- with carry out ?

Result1 <= (’0’ & A) + (’0’ & B)

- For a smaller result, take slices of input arrays

Result2 <= A(6 downto 0) + B(6 downto 0) ;

Length of result depends on length of operands and the operation being performed.

1 Y <= A;

- Y’Length = A’Length

2 Y <= A and B; -- Y’Length = A’Length = B’Length 3 W <= A > B;

- Boolean: W is one bit

4 Y <= A + B;

- Y’Length = Maximum(A’Length, B’Length) or +1 with carry out

5 V <= A * B;

- Y’Length = A’Length + B’Length

SLIDE 7

Type Conversions

The std_logic_vector, unsigned, and signed types are defined as arrays with elements of std_logic. They are not the same type as the built-in boolean, integer, and natural, types, but sometimes it is necessary to work with combinations of these types. There are conversion (typecasting) functions.

Data type of a To data type Conversion function unsigned or signed std_logic_vector std_logic_vector(a) signed or std_logic_vector unsigned unsigned(a) unsigned or std_logic_vector signed signed(a) unsigned or signed integer to_integer(a) natural unsigned to_unsigned(a, size) integer signed to_signed(a, size)

Example:

1 signal a1, a2, a3, a4: std_logic_vector(3 downto 0); 2 signal b1, b2, b3, b4: unsigned(3 downto 0); 3 variable i: natural; 4 ... 5

a1 <= std_logic_vector (b1);

b3 <= unsigned (a4);