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CENG 342 – Digital Systems
Introduction to VHDL Larry Pyeatt
SDSM&T
CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt - - PowerPoint PPT Presentation
CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt - - PowerPoint PPT Presentation
CENG 342 Digital Systems Introduction to VHDL Larry Pyeatt SDSM&T Overview VHDL is a popular language for describing digital hardware and widely used by industry worldwide VHDL is an acronym for VHSIC (Very High Speed Integrated
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1-bit Comparator
Truth Table: i1 i0 eq 1 1 1 1 1 1 Logical function: eq = i1 i0 + i1 i0 Graphical representation:
i0 i1 i0 i0 i1 i0 i1 + i0 i1 i0 i1 i1
VHDL:
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity eq1 is 5
port(
6
i0, i1: in std_logic;
7
eq: out std_logic
8
);
9 end eq1; 10 11 architecture sop_arch of eq1 is 12
signal p0, p1: std_logic;
13 begin 14
- - sum of two product terms
15
eq <= p0 or p1;
16
- - product terms
17
p0 <= (not i0) and (not i1);
18
p1 <= i0 and i1;
19 end sop_arch;
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Fundamentals of VHDL
VHDL syntax is similar to Pascal, Modula 2, Algol, and Ada. Case insensitive: AndGate, andgate, andGate . . . Free formatting: spaces and blank lines can be inserted freely, but it is good practice to make the code clear and readable. Comments: start with -- and any following text in the same line is ignored. Rules of Names (identifier):
Use only letters (a-z or A-Z), digits (0-9) and underscore(_); Must start with a letter. Do not use two or more consecutive underscores (__) within a name All names and labels within a given entity and architecture must be unique Examples: Two_And_Gate, Gate1_and_gate2 . . .
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Example
1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity eq1 is 5
port(
6
i0, i1: in std_logic;
7
eq: out std_logic
8
);
9 end eq1; 10 11 architecture sop_arch of eq1 is 12
signal p0, p1: std_logic;
13 begin 14
- - sum of two product terms
15
eq <= p0 or p1;
16
- - product terms
17
p0 <= (not i0) and (not i1);
18
p1 <= i0 and i1;
19 end sop_arch;
Include libraries. To make programming and maintenance easier, the file name should be the same as the entity name. This file is eq1.vhdl An entity declaration defines the inputs and outputs of an object. An entity may have multiple implemen-
- tations. Each implementation is an “ar-
chitecture”.
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Data Types and Operators
VHDL is a strongly typed language, and allows new data types to be defined. We need a set of data types suitable for synthesis: std_logic is defined in a the IEEE Std 1164 library. To access it, you begin your file with:
1 library ieee; 2 Use ieee.std_logic_1164.all;
The definition provided by the library is as follows:
1 type std_logic is ( ’U’,
- - Uninitialized
2
’X’,
- - Forcing Unknown
3
’0’,
- - Forcing 0
4
’1’,
- - Forcing 1
5
’Z’,
- - High Impedance
6
’W’,
- - Weak Unknown
7
’L’,
- - Weak 0
8
’H’,
- - Weak 1
9
’-’ ); -- Don’t Care This is an example of an enumerated type.
Three of the values 0, 1, and Z, can be synthesized (used in actual circuits). The values U and X may be used in simulation. The other four values are not used in this class.
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Data Types and Operators – Continued
Array of logic values The std_logic_vector data type is defined as an array with elements of std_logic. Example:
1
a: in std_logic_vector(7 downto 0) Defines an array of eight elements a(7), a(6), ...a(0). Logical Operators: not, and, or, xor, nor, xnor, and nand, are defined over the std_logic and std_logic_vector data types. These operators have equal precedence, so you must use parenthesis to specify the desired order of evaluation. For example: (A and B) or (C and D)
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Entities
An entity declaration defines the signals that connect this object to other objects. Syntax:
1 entity entity_name is 2
port (
3
port_name_list : port_mode data_type;
4
port_name_list : port_mode data_type;
5
.............
6
port_name_list : port_mode data_type;
7
port_name_list : port_mode data_type
8
);
9 end entity_name;
Note: no semicolon after the last port declaration, the last semicolon is located outside the parenthesis. Example:
4 entity eq1 is 5
port(
6
i0, i1: in std_logic;
7
eq: out std_logic
8
);
9 end eq1;
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Architectures
An architecture describes the implementation/operation of the circuit Each entity can have multiple architectures Syntax:
1 architecture architecture_name of entity_name is 2 declarations
- - (optional)
3 begin 4
- - code
5 end architecture_name;
Example:
11 architecture sop_arch of eq1 is 12
signal p0, p1: std_logic;
13 begin 14
- - sum of two product terms
15
eq <= p0 or p1;
16
- - product terms
17
p0 <= (not i0) and (not i1);
18
p1 <= i0 and i1;
19 end sop_arch;
Note that the signals do not have to be assigned values in sequential order. This is declarative programming.
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