[PPT] - CENG 342 Digital Systems Routing with a Process Larry Pyeatt PowerPoint Presentation

SLIDE 1

CENG 342 – Digital Systems

Routing with a Process Larry Pyeatt

SDSM&T

SLIDE 2

Process

Statements inside a process are written as if they will be executed sequentially. The process is actually a concurrent statement (or set of concurrent statements). For synthesis, two main purposes:

Describe routing structures with if and case statements Construct templates for memory elements (Chapter 4)

1 process(b, c) 2 begin 3

a <=b and c;

4

a <=c;

5 end process;

The items in the parentheses (b, and c) are the sensitivity list. Each time one of them changes, the process runs. For a combinational circuit, all the input signals should be included in the sensitivity

list. When a signal is assigned multiple times inside a process, only the last one takes

effect.

SLIDE 3

Routing circuit with if statements

if statement syntax:

1 if boolean1 then 2

sequental_statement(s);

3 elsif boolean2 then 4

sequential_statement(s);

5 ... 6 else 7

sequential_statement(s);

8 end if;

SLIDE 4

Priority encoder (3rd approach)

r4 r3 r2 r1 f2 f1 f0 1 1 1

1

1

1

1 1

1

30 architecture if_arch of prio_encoder is 31 begin 32

process(r)

33

begin

34

if (r(4)=’1’) then

35

pcode <= "100";

36

elsif (r(3)=’1’)then

37

pcode <= "011";

38

elsif (r(2)=’1’)then

39

pcode <= "010";

40

elsif (r(1)=’1’)then

41

pcode <= "001";

42

else

43

pcode <= "000";

44

end if;

45

end process;

46 end if_arch;

SLIDE 5

Binary Decoder (3rd approach)

en a1 a0 Q0 Q1 Q2 Q3

1

1 1 1 1 1 1 1 1 1 1 1

33 architecture if_arch of decoder_2_4 is 34 begin 35

process(en,a)

36

begin

37

if (en=’0’) then

38

y <= "0000";

39

elsif (a="00") then

40

y <= "0001";

41

elsif (a="01")then

42

y <= "0010";

43

elsif (a="10")then

44

y <= "0100";

45

else

46

y <= "1000";

47

end if;

48

end process;

49 end if_arch;

SLIDE 6

Routing circuit with case statements

case statement syntax:

1 case sel is 2

when choice(s) =>

3

sequential_statement(s);

4

when choice(s) =>

5

sequential_statement(s);

6

...

7

when others

8

sequential_statement(s);

9 end case

Multiple choices are separated by the pipe (|) character.

SLIDE 7

Priority encoder (4th approach)

r4 r3 r2 r1 f2 f1 f0 1 1 1

1

1

1

1 1

1

48 architecture case_arch of prio_encoder is 49 begin 50

process(r)

51

begin

52

case r is

53

when "1000"|"1001"|"1010"|"1011"|

54

"1100"|"1101"|"1110"|"1111" =>

55

pcode <= "100";

56

when "0100"|"0101"|"0110"|"0111" =>

57

pcode <= "011";

58

when "0010"|"0011" =>

59

pcode <= "010";

60

when "0001" =>

61

pcode <= "001";

62

when others =>

63

pcode <= "000";

64

end case;

65

end process;

66 end case_arch;

SLIDE 8

Binary Decoder (4th approach)

en a1 a0 Q0 Q1 Q2 Q3

1

1 1 1 1 1 1 1 1 1 1 1

51 architecture case_arch of decoder_2_4 is 52

signal s: std_logic_vector(2 downto 0);

53 begin 54

s <= en & a;

55

process(s)

56

begin

57

case s is

58

when "000"|"001"|"010"|"011" =>

59

y <= "0000";

60

when "100" =>

61

y <= "0001";

62

when "101" =>

63

y <= "0010";

64

when "110" =>

65

y <= "0100";

66

when others =>

67

y <= "1000";

68

end case;

69

end process;

70 end case_arch;

SLIDE 9

Comparisons

The if and case statements are equivalent to conditional signal assignment and selected signal assignment, respectively. However, if and case are more flexible and sometimes more efficient. Example: sort the values of two inputs and route them to the large and small outputs

1 -- Two greater-than comparators are needed to synthesize the 2 -- following using conditional signal assignment 3

Large <= a when a>b else b;

4

Small <= b when a>b else a;

1 -- One greater-than comparator is needed to synthesize the 2 -- circuit using a process 3 -- note: process construct is required, but omitted here 4 if a>b then 5

large <=a;

6

small <=b;

7

else

8

large <=b;

9

small <=a;

10

end if ;

SLIDE 10

Comparisons

Example: find the maximal value of three inputs

1 max <= a when ((a>b) and (a>c)) else 2

c when (a>b) else

3

b when (b>c) else

4

a;

1 process(a, b, c) 2 begin 3

if (a>b) then

4

if (a>c) then

5

max <= a;

6

else

7

max <= c;

8

end if

9

else

10

if (b>c) then

11

max <= b;

12

else

13

max <= c;

14

end if;

15

end if;

16 end process;

SLIDE 11

Rules for Processes

Good coding habits:

Include all input signals in the sensitivity list; Include the else branch in an if statement; Assign a value to every signal in every branch: VHDL standard specifies a signal keeps its previous value if it is not assigned in a process;

Example: NOT GOOD! Process should run when b changes, and set values

n all signals.

1

process (a)

2

begin

3

if (a>b) then

4

gt <=’1’;

5

elsif (a=b) then

6

eq <=’1’;

7

end if;

8

end process; OK

1 process (a, b) 2 begin 3

if (a>b) then

4

gt <=’1’;

5

eq <=’0’;

6

elsif (a=b) then

7

gt <=’0’;

8

eq <=’1’;

9

else

10

gt <=’0’;

11

eq <=’0’;

12

end if;

13 end process;

VERY GOOD! Assign defaults and minimize conditional bodies

1 process (a, b) 2 begin 3

gt <=’0’;

4

eq <=’0’;

5

if (a>b) then

6

gt <=’1’;

7

elsif (a=b) then

8

eq <=’1’;

9

end if;

10 end process;