CENG 342 Digital Systems LED Time-multiplexing Larry Pyeatt - - PowerPoint PPT Presentation

CENG 342 – Digital Systems

LED Time-multiplexing Larry Pyeatt

SDSM&T

7-segment Display

The Nexys A7 board has eight 7-segment LED displays. They share 8 signals specifying which segments to light, and each display has its own anode which controls whether or not its segments are lit. Time-multiplexing is a method where we light each LED, one at a time, in rapid

• succession. If if the “refresh rate” is high enough, then it appears to the human eye

that all of the LEDs are continuously illuminated. Any rate above 60 Hz is adequate, but the higher the rate, the more power is

• dissipated. We will try for around 95 Hz.

Time Multiplexing

Basic idea: 3-bit control signal to control 8-to-1 multiplexing and generate active-low enable signals (anx). Can we just use a 3-bit binary counter and feed its outputs into a mux and a decoder? The proper rate is around 100 Hz. The A7 board has a built-in 100 MHz clock. We can use the 100 MHz clock, but how do we reduce a 100 MHz clock to around 100 Hz? A binary counter is a good tool to achieve this goal. How many bits are needed in the binary counter? In the design, 100MHz

100Hz = 1000000. This indicates we need to divide by about one

• million. How many bits gives us a count of about 1 million?

an0 an1 an2 an3 an4 an5 an6 an7 a b c d e f g dp

Component Schematic

data_out sseg_out select

3 to 8 Decoder Hex to 7-segment Decoder 5×8 Register File

• ut0
• ut1
• ut2
• ut3
• ut4
• ut5
• ut6

Counter

in_select data_in Address Data_In an0 an1 an2 an3 an4 an5 an6 an7 sseg

7-Segment Display Controller

hex_in

• ut_select

5 3 5 8 3 Clock Reset enable Write Enable Reset write reset

• ut7

enable

Register File

Array of 5-bit registers Decoder (with enable) to enable register for writing Mux to select register for output

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 package my_package is 6

type slv_array_5 is array(natural range <>) of std_logic_vector(4 downto 0);

7

type slv_array_8 is array(natural range <>) of std_logic_vector(7 downto 0);

8

type slv_array_16 is array(natural range <>) of std_logic_vector(15 downto 0);

9 end package;

Multiplexor

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 use work.my_package.all; 5 6 entity generic_mux_5 is 7

generic(sel_bits:integer:=1);

• - number of selector bits

8

port(

9

sel: in std_logic_vector(sel_bits

• 1 downto 0);
• - selector inputs

10

d_in:in slv_array_5(2**sel_bits

• 1 downto 0);

11

Y:

• ut std_logic_vector(4 downto 0)

12

);

13 end generic_mux_5; 14 15 architecture arch of generic_mux_5 is 16 begin 17

process(sel,d_in)

18

variable sel_n:natural;

19

begin

20

sel_n := to_integer(unsigned(sel));

21

Y <= d_in(sel_n);

22

end process;

23 end arch;

Decoder

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_decoder is 6

generic(

7

bits:integer:=1

• - number of selector inputs

8

);

9

port(

10

sel: in std_logic_vector(bits-1 downto 0); -- selector inputs

11

Y:

• ut std_logic_vector(2**bits-1 downto 0)

12

);

13 end generic_decoder; 14 15 architecture arch of generic_decoder is 16 begin 17

process(sel)

18

variable sel_n:natural;

19

begin

20

Y <= (others=>’1’);

21

sel_n := to_integer(unsigned(sel));

22

Y(sel_n) <= ’0’;

23

end process;

Decoder with Enable

29 library ieee; 30 use ieee.std_logic_1164.all; 31 use ieee.numeric_std.all; 32 33 entity generic_decoder_with_enable is 34

generic( bits:integer:=1 );

• - number of selector inputs

35

port(

36

en: in std_logic;

37

sel: in std_logic_vector(bits-1 downto 0); -- selector inputs

38

Y:

• ut std_logic_vector(2**bits-1 downto 0)

39

);

40 end generic_decoder_with_enable; 41 42 architecture arch of generic_decoder_with_enable is 43 begin 44

process(en,sel)

45

variable sel_n:natural;

46

begin

47

if en=’1’ then

48

Y <= (others=>’1’);

49

else

50

Y <= (others=>’1’);

51

sel_n := to_integer(unsigned(sel));

52

Y(sel_n) <= ’0’;

53

end if;

54

end process;

55 end arch;

Register

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_register is 6

generic(bits:integer:=4);

• - number of bits

7

port( en: in std_logic;

• - active low enable

8

clk: in std_logic;

• - rising edge-triggered

9

reset:in std_logic;

• - active low asynchronous reset

10

d: in std_logic_vector(bits-1 downto 0);

11

q:

• ut

std_logic_vector(bits-1 downto 0));

12 end generic_register; 13 14 architecture arch of generic_register is 15

signal latched_data:std_logic_vector(bits-1 downto 0);

16 begin 17

process(en,clk,reset)

18

begin

19

if reset = ’0’ then

20

latched_data <= (others => ’0’);

21

else

22

if en=’0’ and clk’event and clk=’1’ then

23

latched_data <= d;

24

end if;

25

end if;

26

end process;

27

q<=latched_data;

28 end arch;

Register File – Entity Declaration

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 use work.my_package.all; 5 6 entity generic_register_file_5 is 7

generic(n_sel:integer:=1); -- number of bits for selecting a register

8

port(

9

en: in std_logic;

• - active low enable

10

clk: in std_logic;

• - rising edge-triggered

11

rst: in std_logic;

• - active low asynchronous reset

12

dsel: in std_logic_vector(n_sel-1 downto 0);

13

d: in std_logic_vector(4 downto 0);

14

qsel: in std_logic_vector(n_sel-1 downto 0);

15

q:

• ut

std_logic_vector(4 downto 0)

16

);

17 end generic_register_file_5;

Register File – Architecture

19 architecture arch of generic_register_file_5 is 20

signal enable:std_logic_vector(2**n_sel-1 downto 0);

21

signal reg_data:slv_array_5(2**n_sel-1 downto 0);

22 begin 23

regs: for i in 0 to 2**n_sel -1 generate

24

reg: entity work.generic_register(arch)

25

generic map(bits=>5)

26

port map(en=>enable(i),clk=>clk,reset=>rst,d=>d,q=>reg_data(i));

27

end generate regs;

28 29

• utmux: entity work.generic_mux_5(arch)

30

generic map(sel_bits=>n_sel)

31

port map(sel=>qsel,d_in=>reg_data,Y=>q);

32 33

indec: entity work.generic_decoder_with_enable(arch)

34

generic map(bits=>n_sel)

35

port map(en=>en,sel=>dsel,y=>enable);

36 37 end arch;

Component Schematic

data_out sseg_out select

3 to 8 Decoder Hex to 7-segment Decoder 5×8 Register File

• ut0
• ut1
• ut2
• ut3
• ut4
• ut5
• ut6

Counter

in_select data_in Address Data_In an0 an1 an2 an3 an4 an5 an6 an7 sseg

7-Segment Display Controller

hex_in

• ut_select

5 3 5 8 3 Clock Reset enable Write Enable Reset write reset

• ut7

enable

Hex to 7-segment Decoder

1 library ieee; 2 use ieee.std_logic_1164.all; 3 4 entity hex_to_sseg is 5

port( hex: in std_logic_vector(3 downto 0);

6

dp: in std_logic;

7

sseg: out std_logic_vector(7 downto 0));

8 end hex_to_sseg; 9 10 architecture arch of hex_to_sseg is 11 begin 12

with hex select

13

sseg(6 downto 0) <=

14

"1000000" when "0000", "1111001" when "0001",

15

"0100100" when "0010", "0110000" when "0011",

16

"0011001" when "0100", "0010010" when "0101",

17

"0000010" when "0110", "1111000" when "0111",

18

"0000000" when "1000", "0011000" when "1001",

19

"0001000" when "1010", "0000011" when "1011",

20

"1000110" when "1100", "0100001" when "1101",

21

"0000110" when "1110", "0001110" when others;

22

sseg(7) <= not dp;

23 end arch;

Counter

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_counter is 6

generic(bits:integer:=4);

7

port( clk: in std_logic;

8

rst: in std_logic;

• - asynch reset (active low)

9

q:

• ut std_logic_vector(bits-1 downto 0));

10 end generic_counter; 11 12 architecture arch of generic_counter is 13

signal data:unsigned(bits-1 downto 0);

14 begin 15

process(clk,rst)

16

begin

17

if rst = ’0’ then

18

data <= (others => ’0’);

19

else

20

if clk’event and clk = ’1’ then

21

data <= data + 1;

22

end if;

23

end if;

24

end process;

25 26

q <= std_logic_vector(data);

27 28 end arch;

Component Schematic

data_out sseg_out select

3 to 8 Decoder Hex to 7-segment Decoder 5×8 Register File

• ut0
• ut1
• ut2
• ut3
• ut4
• ut5
• ut6

Counter

in_select data_in Address Data_In an0 an1 an2 an3 an4 an5 an6 an7 sseg

7-Segment Display Controller

hex_in

• ut_select

5 3 5 8 3 Clock Reset enable Write Enable Reset write reset

• ut7

enable

7-segment Display Controller – Entity Declaration

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 use work.my_package.all; 5 6 entity hexdisplay is 7

generic(

8

adr_bits:integer:=3;

• - log_2(number of displays)

9

div_bits:integer:=20

• - sets refresh rate (divide by 2**div_bits)

10

);

11

port(

12

en: in std_logic;

• - chip enable

(active low)

13

wr: in std_logic;

• - write enable (active low)

14

reset: in std_logic;

• - asynch reset (active low)

15

address: in std_logic_vector(adr_bits

• 1 downto 0); -- address

16

data_in: in std_logic_vector(7 downto 0); -- dp is on data(5)

17

clock : in std_logic;

• - clock

18

sseg: out std_logic_vector(7 downto 0);

• - segment drivers

19

an: out std_logic_vector(2**adr_bits

• 1 downto 0) -- anodes

20

);

21 end hexdisplay;

7-segment Display Controller – Architecture

24

signal count:std_logic_vector(div_bits

• 1 downto 0);

25

signal to_7seg_decoder:std_logic_vector(4 downto 0);

26 begin 27 28

• - a set of registers

29

regs: entity work.generic_register_file_5(arch)

30

generic map(n_sel=>adr_bits)

31

port map(en=>en, clk=>wr, rst=>reset, dsel=>address,d=>data_in(4 downto 0),

32

qsel=>count(div_bits

• 1 downto div_bits-adr_bits),q=>to_7seg_decoder);

33 34

• - a 7-segment decoder to convert data in the registers to signals

35

• - for the 7-segment displays

36

ssdec: entity work.hex_to_sseg(arch)

37

port map(hex=>to_7seg_decoder(3 downto 0),dp=>to_7seg_decoder(4),sseg=>sseg);

38 39

• - a decoder to select the 7-segment display anode

40

andec: entity work.generic_decoder(arch)

41

generic map(bits=>adr_bits)

42

port map(sel=>count(div_bits

• 1 downto div_bits-adr_bits),Y=>an);

43 44

• - a counter to control switching between the displays

45

cnt: entity work.generic_counter(arch)

46

generic map(bits=>div_bits)

47

port map(clk=>clock,rst=>reset,q=>count);

48 49 end arch;

Multiplexor Testbench

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 use work.my_package.all; 5 6 entity generic_mux_5_testbench is 7 end generic_mux_5_testbench; 8 9 architecture arch of generic_mux_5_testbench is 10

signal en:std_logic;

11

signal sel:std_logic_vector(1 downto 0);

12

signal in0: std_logic_vector(4 downto 0) := "00001";

13

signal in1: std_logic_vector(4 downto 0) := "00010";

14

signal in2: std_logic_vector(4 downto 0) := "00011";

15

signal in3: std_logic_vector(4 downto 0) := "11111";

16

signal output:std_logic_vector(4 downto 0);

17

signal testin: unsigned(2 downto 0):="000";

Multiplexor Testbench – part 2

19 begin 20

uut: entity work.generic_mux_5(arch)

21

generic map(sel_bits=>2)

22

port map(en=>en, sel => sel, Y => output,

23

d_in(0)=>in0,

24

d_in(1)=>in1,

25

d_in(2)=>in2,

26

d_in(3)=>in3

27

);

28 29

process

30

begin

31

loop

32

wait for 10 ns;

33

testin <= testin + 1;

34

end loop;

35

end process;

36 37

sel <= std_logic_vector(testin(2 downto 1));

38

en <= testin(0);

39 40 41 end arch;

Decoder with Enable Testbench

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_decoder_testbench is 6 end generic_decoder_testbench; 7 8 architecture arch of generic_decoder_testbench is 9

signal en:std_logic;

10

signal sel:std_logic_vector(2 downto 0);

11

signal output:std_logic_vector(7 downto 0);

12

signal testin: unsigned(3 downto 0):="0000";

13 begin 14

uut: entity work.generic_decoder_with_enable(arch)

15

generic map(bits=>3)

16

port map(en=>en, sel => sel, Y => output);

17

process

18

begin

19

loop

20

wait for 10 ns;

21

testin <= testin + 1;

22

end loop;

23

end process;

24

sel <= std_logic_vector(testin(3 downto 1));

25

en <= testin(0);

26 end arch;

Register Testbench

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_register_testbench is 6 end generic_register_testbench; 7 8 architecture arch of generic_register_testbench is 9

signal qout:std_logic_vector(1 downto 0);

10

signal control:unsigned(4 downto 0):="00000";

11

signal reset:std_logic:=’1’;

12

signal din:std_logic_vector(1 downto 0);

13

signal clock,enable:std_logic;

14 begin 15

uut: entity work.generic_register(arch)

16

generic map(bits=>2)

17

port map(en=>enable,clk=>clock,reset=>reset,d=>din,q=>qout);

18 19

process

20

begin

21

wait for 10 ns;

22

reset <= ’0’;

23

wait for 10 ns;

24

reset <= ’1’;

25

wait;

26

end process;

Register Testbench – part 2

28

process

29

begin

30

loop

31

wait for 10 ns;

32

control <= control + 1;

33

end loop;

34

end process;

35 36

din <= std_logic_vector(control(4 downto 3));

37

clock<=control(0);

38

enable<=control(2);

39 40 end arch;

Register File Testbench

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_register_file_5_testbench is 6 end generic_register_file_5_testbench; 7 8 architecture arch of generic_register_file_5_testbench is 9

signal qout:std_logic_vector(4 downto 0);

10

signal control:unsigned(4 downto 0):="00000";

11

signal inselect: std_logic_vector (1 downto 0):="00";

12

signal outselect: std_logic_vector (1 downto 0):="00";

13

signal reset:std_logic:=’1’;

14

signal din:std_logic_vector(4 downto 0);

15

signal clock,enable:std_logic:=’1’;

16 begin 17

uut: entity work.generic_register_file_5(arch)

18

generic map(n_sel=>2)

19

port map(en=>enable,clk=>clock,rst=>reset,dsel=>inselect,d=>din,qsel=>outselect,q=>qout);

20 21

process

22

begin

23

wait for 10 ns;

24

reset <= ’0’;

25

wait for 10 ns;

26

reset <= ’1’;

27

wait;

28

end process;

Register File Testbench – part 2

30

process

31

begin

32

wait for 5 ns;

33

clock <= not clock;

34

loop

35

wait for 10 ns;

36

clock <= not clock;

37

end loop;

38

end process;

39 40

process

41

variable dat,i:natural:=0;

42

begin

43

loop

44

for i in 0 to 3 loop

45

inselect <= std_logic_vector(to_unsigned(i,2));

46

din <= std_logic_vector(to_unsigned(dat,5));

47

dat := dat + 1;

48

enable <= ’0’;

49

wait for 10 ns;

50

enable <= ’1’;

51

end loop;

52

for i in 0 to 3 loop

53

• utselect <= std_logic_vector(to_unsigned(i,2));

54

wait for 10 ns;

55

end loop;

56

end loop;

57

end process;

58 end arch;

Counter Testbench

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity generic_counter_testbench is 6 end generic_counter_testbench; 7 8 architecture arch of generic_counter_testbench is 9

signal clock:std_logic := ’1’;

10

signal reset:std_logic := ’1’;

11

signal output:std_logic_vector(4 downto 0);

12 begin 13

uut: entity work.generic_counter(arch)

14

generic map(bits=>5)

15

port map(clk=>clock,rst=>reset,q=>output);

16 17

process

18

begin

19

wait for 10 ns;

20

reset <= ’0’;

21

wait for 10 ns;

22

reset <= ’1’;

23

wait;

24

end process;

Counter Testbench – part 2

26

process

27

begin

28

wait for 5 ns;

29

clock <= not clock;

30

loop

31

wait for 10 ns;

32

clock <= not clock;

33

end loop;

34

end process;

35 36 end arch;

7-segment Display Controller Testbench

1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity hexdisplay_testbench is 6 end hexdisplay_testbench; 7 8 architecture arch of hexdisplay_testbench is 9

signal en: std_logic:=’1’;

• - chip enable

(active low)

10

signal wr: std_logic:=’1’;

• - write enable (active low)

11

signal reset: std_logic:=’1’;

• - asynch reset (active low)

12

signal clock: std_logic:=’1’;

• - clock

13

signal address: std_logic_vector(2 downto 0):="000";

14

signal data_in: std_logic_vector(7 downto 0):="00000000";

15

signal sseg: std_logic_vector(7 downto 0):="00000000";

16

signal an: std_logic_vector(7 downto 0):="00000000";

17

signal data_count:unsigned(7 downto 0) := "00000000" ;

18 19 begin 20

disp: entity work.hexdisplay(arch)

21

generic map(adr_bits=>3,div_bits=>3)

22

port map(en => en, wr => wr, reset => reset, clock => clock,

23

address => address, data_in => data_in, sseg => sseg, an => an);

7-segment Display Controller Testbench – part 2

25

process

26

variable i:natural;

27

begin

28

wait for 30 ns;

29

loop

30

for i in 0 to 7 loop

31

data_in <= std_logic_vector(data_count);

32

address <= std_logic_vector(to_unsigned(i,3));

33

en<=’0’;

34

wait for 2 ns;

35

wr<=’0’;

36

wait for 5 ns;

37

en<=’1’;

38

wr<=’1’;

39

data_count <= data_count + 1;

40

end loop;

41

wait for 400ns;

42

end loop;

43

end process;

7-segment Display Controller Testbench – part 3

45

process

46

begin

47

wait for 10 ns;

48

reset <= ’0’;

49

wait for 10 ns;

50

reset <= ’1’;

51

wait;

52

end process;

53 54

process

55

begin

56

wait for 5 ns;

57

loop

58

clock <= not clock;

59

wait for 10 ns;

60

end loop;

61

end process;

62 63 64 end arch;