SLIDE 1
CENG 342 – Digital Systems
Constants and Generics Larry Pyeatt
SDSM&T
CENG 342 Digital Systems Constants and Generics Larry Pyeatt - - PowerPoint PPT Presentation
CENG 342 Digital Systems Constants and Generics Larry Pyeatt - - PowerPoint PPT Presentation
CENG 342 Digital Systems Constants and Generics Larry Pyeatt SDSM&T 4-to-1 Mulitplexer Schematic and Truth Table Boolean function: F = i 0 sel 1 sel 0 + i 1 sel 1 sel 0 + i 2 sel 1 sel 0 + i 3 sel 1 sel 0 Routing circuits Conditional
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2-bit Comparator
a1 a0 b1 b0 gt lt eq 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity cmp_2bit is 6
port( a : in unsigned(1 downto 0);
7
b : in unsigned(1 downto 0);
8
lt,gt,eq : out std_logic);
9 end cmp_2bit; 10 11 architecture if_arch of cmp_2bit is 12 begin 13
process(a, b)
14
begin
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lt <= ’0’;
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gt <= ’0’;
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eq <= ’0’;
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if a > b then
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gt <= ’1’;
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else
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if a < b then
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lt <= ’1’;
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else
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eq <= ’1’;
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end if;
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end if;
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end process;
28 end if_arch;
SLIDE 4
Testbench for 2-bit Comparator
Use concurrent processes to toggle the input bits.
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity cmp_2bit_test is 6 end cmp_2bit_test; 7 8 architecture test_arch of cmp_2bit_test is 9
signal t0,t1 : unsigned(1 downto 0);
10
signal eq,lt,gt : std_logic;
11 begin 12
uut: entity work.cmp_2bit(if_arch)
13
port map(a=>t0, b=>t1,
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lt=>lt, gt=>gt, eq=>eq);
15 16
p1: process
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begin
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t1(0) <= ’0’;
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loop
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wait for 50ns;
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t1(0) <= not t1(0);
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end loop;
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end process;
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p2: process
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begin
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t1(1) <= ’0’;
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loop
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wait for 100ns;
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t1(1) <= not t1(1);
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end loop;
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end process;
33 34
p3: process
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begin
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t0(0) <= ’0’;
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loop
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wait for 200ns;
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t0(0) <= not t0(0);
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end loop;
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end process;
42 43
p4: process
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begin
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t0(1) <= ’0’;
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loop
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wait for 400ns;
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t0(1) <= not t0(1);
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end loop;
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end process;
SLIDE 5
Testbench Using Loops
53 architecture loop_test_arch of cmp_2bit_testbench is 54
signal t0,t1 : unsigned(1 downto 0);
55
signal eq,lt,gt : std_logic;
56 begin 57
uut: entity work.cmp_2bit(if_arch)
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port map(a=>t0, b=>t1, lt=>lt, gt=>gt, eq=>eq);
59 60
process1:process
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variable m, n: integer;
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begin
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t0 <= "00";
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t1 <= "00";
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for n in 0 to 3 loop
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t1 <= to_unsigned(n,2);
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for m in 0 to 3 loop
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t0 <= to_unsigned(m,2);
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wait for 50 ns;
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end loop;
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end loop;
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end process;
73 end loop_test_arch;
Many other variations are possible.
SLIDE 6
Simulation Results
SLIDE 7
Variables, Signals, Constants, Generics
Signals are declared at the start of an architecture, and can be used anywhere within that architecture. Signal declaration: signal list_of_names : type_name[:=initial_value]; Signals must be declared within an architecture and their scope (visibility) is local to that architecture. Variables can be declared at the start of a process. Variable declaration: variable list_of_names : type_name[:=initial_value]; Variables must be declared within a process and their scope (visibility) is local to that process. Constants can be declared at the start of an architecture or processes. Constant declaration: constant constant_name : type_name := value; Their scope is the architecture or process where they are declared. Generics can be used to assign desired values in components in other code (will be described shortly).
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Constants
Constants can be used in expressions and for specifying array boundaries. Examples:
1
constant DATA_BIT: integer := 4;
2
constant DATA_RANGE: integer :=2**DATA_BIT
- 1;
Constants can not be changed. Example: 4-bit adder with carry-out
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity add_w_carry is 6
port(
7
a, b: in std_logic_vector(3 downto 0);
8
sum: out std_logic_vector(4 downto 0);
9
);
10 end add_w_carry;
SLIDE 9
Constants – continued
Basic architecture:
12 architecture hard_arch of add_w_carry is 13
signal a_ext, b_ext, sum_ext: unsigned(4 downto 0);
14 begin 15
a_ext <= unsigned(’0’ & a); -- concatenate ’0’ bit to front
16
b_ext <= unsigned(’0’ & b); -- concatenate ’0’ bit to front
17
sum_ext <= a_ext + b_ext;
- - perform addition
18
sum <= std_logic_vector(sum_ext(4 downto 0)); -- type conversion
19 end hard_arch;
Using a constant makes it easier to understand and maintain
21 architecture const_arch of add_w_carry is 22
constant N: integer := 4; -- most significant output bit is 4
23
signal a_ext, b_ext, sum_ext: unsigned(N downto 0);
24 begin 25
a_ext <= unsigned(’0’ & a);
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b_ext <= unsigned(’0’ & b);
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sum_ext <= a_ext + b_ext;
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sum <= std_logic_vector(sum_ext(N downto 0));
29 end const_arch;
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Generics
Generic provides a way to pass information into components at instantiation Can not be modified in the architecture, but can be re-defined in components. Declared inside an entity declaration, just before the port declaration. Syntax:
1 entity entity_name is 2
generic(
3
generic_name: data_type :=value;
4
generic_name: data_type :=value);
5
port( port_declaratons );
6 end entity_name
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Generic Declaration Example
1 library ieee; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity gen_add_w_carry is 6
generic(N: integer:=4);
7
port(a, b: in std_logic_vector(N-1 downto 0);
8
sum: out std_logic_vector(N downto 0));
9 end gen_add_w_carry; 10 11 architecture arch of gen_add_w_carry is 12
signal a_ext, b_ext, sum_ext: unsigned(N downto 0);
13 begin 14
a_ext <= unsigned(’0’ & a);
15
b_ext <= unsigned(’0’ & b);
16
sum_ext <= a_ext + b_ext;
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sum <= std_logic_vector(sum_ext(N downto 0));
18 end arch;
SLIDE 12
Generic Mapping
When the adder is used as a component in other code, the desired value can be assigned to the generic. This is called generic mapping. Generics allow the programmer to design scaleable code. The width of a circuit can be specified to meet a specific need. A generic decoder can be instantiated as an n by 2n
- decoder. A generic mux can be an m-bit 2n-to-1 mux.
Example:
1
signal a4, b4: unsigned (3 downto 0);
2
signal sum5: unsigned (4 downto 0);
3
signal a8, b8: unsigned (7 downto 0);
4
signal sum9: unsigned (8 downto 0);
5 ... 6
- -instantiate 8-bit adder
7
adder_8_unit: work.gen_add_w_carry (arch)
8
generic map (N=>8)
9
port map(a=>a8, b=>b8, sum=>sum9);
10
- -if no generic mapping is given, the default value is used
11
adder_4_unit: work. gen_add_w_carry (arch)
12