14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University - - PDF document

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14:332:231 DIGITAL LOGIC DESIGN

Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013

Lecture #24: Verilog Time Dimension and Test Benches

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Verilog Functions and Tasks

• Verilog function accepts several inputs and returns a

single result

f unct i on result-type function-name ; input declarations variable declarations parameter declarations procedural-statement endf unct i on

• Verilog task is similar to a function, except it does not

return a result

• Built-in system tasks and functions:

– $di spl ay = prints formatted signal values to “standard output” (similar to C pr i nt f function) – $wr i t e = similar to $di spl ay, but no newline char at end – $m

• ni t or = similar to $di spl ay, but remain active continuously

and prints the listed signals whenever any one changes – $t i m e = returns current simulated time

[ behavioral style ]

m

• dul e Vr Si l l i er XO

R ( . . . ) ; port-declarations f unct i on I nhi bi t ; i nput I n, i nvI n; I nhi bi t = I n & ~i nvI n; endf unct i on al ways @ ( i n1 or i n2) begi n i nh1 = I nhi bi t ( i n1, i n2) ; . . . . . . end m

• dul e Vr Si l l i er XO

R ( . . . ) ; port-declarations f unct i on I nhi bi t ; i nput I n, i nvI n; I nhi bi t = I n & ~i nvI n; endf unct i on al ways @ ( i n1 or i n2) begi n i nh1 = I nhi bi t ( i n1, i n2) ; . . . . . . end

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Abstract Model Functionality

• Abstract functionality is

represented using procedures

• Begin with the keywords

i ni t i al or al ways

– An i ni t i al procedure will execute once, beginning at simulated time zero – al ways procedures model the continuous

• peration of hardware
• Procedures contain

programming statements

• Multiple statements are

grouped with begi n and end

m

• dul e Ful l Adder ( i nput

wi r e a, i nput wi r e b, i nput wi r e ci ,

• ut put r eg sum

, co) ; i ni t i al begi n sum = 0; co = 0; end al ways @ ( a or b or ci ) begi n { co, sum } = a + b + ci ; end endm

• dul e

[ behavioral style ]

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Procedural Block Activation

• All concurrent statements (procedures) automatically

become active at time zero

• Note: Verilog procedures are not like software

subroutines, which must be called in order to be activated

i ni t i al begi n a = 0; b = 0; #10 a = 1; . . . end i ni t i al begi n a = 0; b = 0; #10 a = 1; . . . end i ni t i al begi n sum = 0; end i ni t i al begi n sum = 0; end al ways @ ( a or b) begi n sum = a + b; end al ways @ ( a or b) begi n sum = a + b; end al ways @ ( posedge cl k) begi n q <= sum ; end al ways @ ( posedge cl k) begi n q <= sum ; end

Time 0

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Verilog Time Scale

• Default time scale is 1 ps (picoseconds), but can

be changed using the `timescale compiler directive

` t i m escal e time-unit / time-precision – Example:

` t i m escal e 1 ns / 100 ps m

• dul e Vr pr i m

edl y ( N, F) ; . . . / / W aker l y, Tabl e 5- 97, page 330 assi gn #2 N3L_No = ~N[ 3] ;

• In procedural blocks of code, delays specified by

writing # symbol and a delay number:

– At the start of an al ways block (seen in the next slide) – After the = or <= symbol in a procedural assignment

[ [ Verilog Verilog time dimension ] time dimension ]

2 ns delay for the assi gn statement’s operation 6 of 10

Controlling Verilog Procedures

• i ni t i al and al ways procedures may contain 3 types of timing:
• 1. Time based delays — the # token

– Delays execution of the next statement for a specific amount of time al ways / / del ayed f or 2 si m ul at i on t i m e uni t s #2 sum = a + b;

• 2. Edge sensitive delays — the @ token

– Delays execution of the next statement until a change occurs on a signal al ways / / del ayed unt i l posi t i ve edge of cl ock @ ( posedge cl ock) sum <= a + b;

• 3. Level sensitive delays — the wai t keyword

– Delays execution of the next statement until a logic test evaluates as TRUE al ways / / del ayed unt i l ' enabl e' becom es ' 1' wai t ( enabl e == 1) sum = a + b;

• Each time control delays execution of the next statement or statement

group

[ [ Verilog Verilog time dimension ] time dimension ]

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Verilog Test Benches

• Unit under test (UUT) = the entity/module being tested

– Also called Device under test (DUT)

• Verilog Test Bench consists of:

– UUT – UUT stimulus, to provide inputs to the UUT – UUT monitor, to capture and analyze the UUT output Verilog UUT UUT Stimulus UUT Monitor Verilog Test Bench inputs

• utputs

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Example Verilog Test Bench (1)

• Unit under test: mux2

(described in Lecture #23)

/ * 2- i nput m ul t i pl exor t est bench #1 * / ` t i m escal e 1 ns / 100 ps m

• dul e m

ux2_t b1 ( ) ; wi r e m _out ; r eg m _sel , m _i n0, m _i n1; m ux2 m 2_uut ( m _i n0, m _i n1, m _sel , m _out ) ; i ni t i al begi n m _i n0 = 1' b0; m _i n1 = 1' b0; m _sel = 1' b0; $di spl ay ( " t i m e: % d, out put : % d" , $t i m e, m _out ) ; #5 / / wai t 5 ns bef or e cont i nui ng m _i n0 = 1' b1; m _sel = 1' b1; $di spl ay ( " t i m e: % d, out put : % d" , $t i m e, m _out ) ; $f i ni sh; / / t ask cal l ends si m ul at i on end endm

• dul e / / m

ux2_t b1

/ * 2- i nput m ul t i pl exor i n gat es * / m

• dul e m

ux2 ( i n0, i n1, sel ect , out ) ; i nput i n0, i n1, sel ect ;

• ut put out ;

wi r e s0, w0, w1; not ( s0, sel ect ) ; and ( w0, s0, i n0) , ( w1, sel ect , i n1) ;

• r ( out , w0, w1) ;

endm

• dul e / / m

ux2

Two concurrent statements:

• Instance statement
• i ni t i al procedure

Both automatically become active at time zero The i ni t i al procedure changes the input values for UUT as it runs continuously Note blocking assignments

• ut

in1 in0 select 1

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• Now, all the data is

stored in “test_vectors.”

• The most significant

bit, is assigned to “in0”, the next to “in1” and the last to “select”.

• In the second

i ni t i al block, we generate all the test vectors, 000 through 111, in a f or loop.

• Note that the #5 waits

5 ns before going to the next test vector.

Example Verilog Test Bench (2)

• Generating Test Vectors

/ * 2- i nput m ul t i pl exor t est bench #2 * / ` t i m escal e 1 ns / 100 ps m

• dul e m

ux2_t b2 ( ) ; wi r e m _out ; r eg [ 2: 0] t est _vect or s; / / 3- bi t wi de t est vect or i nt eger i ; m ux2 m 2_uut ( . i n0( t est _vect or s[ 2] ) , . i n1( t est _vect or s[ 1] ) , . sel ect ( t est _vect or s[ 0] ) , . out ( m _out ) ) ; i ni t i al begi n / / i ni t i al i ze al l var i abl es t est _vect or s = 3' b000; end i ni t i al begi n f or ( i =0; i <7; i =i +1) begi n #5 / / wai t 5 ns bef or e cont i nui ng t est _vect or s = t est _vect or s + 1; $di spl ay ( " t i m e: % d, out put : % d" , $t i m e, m _out ) ; end end endm

• dul e / / m

ux2_t b2

• ut

in1 in0 select 1

/ * 2- i nput m ul t i pl exor i n gat es * / m

• dul e m

ux2 ( i n0, i n1, sel ect , out ) ; i nput i n0, i n1, sel ect ;

• ut put out ;

wi r e s0, w0, w1; not ( s0, sel ect ) ; and ( w0, s0, i n0) , ( w1, sel ect , i n1) ;

• r ( out , w0, w1) ;

endm

• dul e / / m

ux2

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Self-Checking Test Bench

• SystemVerilog asser t

statement checks if specified condition is true; if not, it executes the el se statement

• The $er r or

system task prints and error message describing the assertion failure / * 2- i nput m ul t i pl exor t est bench #3 * / ` t i m escal e 1 ns / 100 ps m

• dul e m

ux2_t b3 ( ) ; wi r e m _out ; r eg m _sel , m _i n0, m _i n1; m ux2 m 2_uut ( m _i n0, m _i n1, m _sel , m _out ) ; i ni t i al begi n m _i n0 = 1' b0; m _i n1 = 1' b0; m _sel = 1' b0; asser t ( m _out === 0 ) el se $er r or ( " 000 f ai l ed" ) ; #5 / / wai t 5 ns m _i n0 = 1' b1; m _sel = 1' b1; / / sel ect s m _i n1, whi ch i s 1' b0 asser t ( m _out === 0 ) el se $er r or ( " 101 f ai l ed" ) ; $f i ni sh; end endm

• dul e / / m

ux2_t b3