14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University - - PDF document

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14:332:231 DIGITAL LOGIC DESIGN

Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013

Lecture #13: Digital Comparators

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Digital Comparators

• Comparator: A circuit that compares two

binary words and indicates whether they are equal

• Magnitude comparator: Interprets its

inputs as signed or unsigned numbers and indicates their arithmetic relationship (greater or less than)

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Example Comparator Use

• Devices are enabled by comparing a “device

select” word with a predetermined “device ID”

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Equality Comparators

• 1-bit comparator
• Active-high output

(DIFF) asserted if the inputs are different

• 4-bit comparator
• The DIFF output is

asserted if any of the input pairs are different

A0 B0 DIFF

1/4 74x86

1 2 3

U1

EQ_L

A0 B0 DIFF0

74x86

1 2 3

U1 A1 B1 DIFF1

4 5 6

U1 A2 B2 DIFF2

9 10 8

U1 A3 B3 DIFF3

12 13 11

U1 DIFF

EQ_L

3

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4-Bit Magnitude Comparator

• Two input numbers to compare, 4 bits each: A=A3A2A1A0 ; B=B3B2B1B0
• Three outputs, reporting “greater than”, “less than”, and “equal”, respectively

1 A0 = B0 A1 = B1 A2 = B2 A3 = B3 1 A0 = B0 A1 = B1 A2 = B2 A3 = B3 1 A0 = B0 A1 = B1 A2 = B2 A3 = B3 1 A0 < B0 A1 = B1 A2 = B2 A3 = B3 1 A0 > B0 A1 = B1 A2 = B2 A3 = B3 1 x A1 < B1 A2 = B2 A3 = B3 1 x A1 > B1 A2 = B2 A3 = B3 1 x x A2 < B2 A3 = B3 1 x x A2 > B2 A3 = B3 1 x x x A3 < B3 1 1 x x x A3 > B3 “A = B” “A < B” “A > B” A0, B0 A1, B1 A2, B2 A3, B3 Outputs Compared Inputs Note “x” (don’t care) notation. 6 of 12

4-Bit Magnitude Comparator

• Input A=A3A2A1A0 ; B=B3B2B1B0
• Case A = B : A3=B3, A2=B2, A1=B1, A0=B0

xi = (AiBi) = Ai·Bi + Ai·Bi

XNOR = (AiBi) = (Ai·Bi+ Ai·Bi) = (Ai+Bi)·(Ai+Bi) = Ai·Ai + Ai·Bi + Ai·Bi + Bi·Bi = Ai·Bi + Ai·Bi

– Output: x3·x2·x1·x0

• Case A > B :

– Output: A3·B3 + x3·A2·B2 + x3·x2·A1·B1 + x3·x2·x1·A0·B0

• Case A < B :

– Output: A3·B3 + x3·A2·B2 + x3·x2·A1·B1+ x3·x2·x1·A0·B0

(A<B) (A>B) (A=B)

A3 B3 A2 B2 A1 B1 A0 B0 x3 x2 x1 x0

XNOR

X Y (XY)

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Iterative Combinational Circuits

• General structure: n identical modules

– For problems that can be solved by an iterative algorithm:

1. Set C0 to its initial value and set i to 0 2. While i < n repeat:

a) Use Ci an PIi to determine the values of POi and Ci+1 b) Increment i a

PI PO CI CO module C0 PI0 C1 PO0 boundary inputs cascading input cascading

• utput

PI PO CI CO module PI1 C2 PO1 PI PO CI CO module Cn POn–1 boundary

• utputs

PIn–1 Cn–1 primary inputs primary outputs

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An Iterative Comparator Circuit

• (a) module for one bit
• (b) complete circuit

– Comparing two n-bit values X and Y:

• 1. Set EQ0 to 1 and set i to 0
• 2. While i < n repeat:

a) If EQi is 1 and Xi equals Yi, set EQi+1 to 1 Else set EQi+1 to 0 b) Increment i

• Slow because the cascading signals

need time to “ripple” from left to right

first input has to be 1

EQO = (A  B) · EQI

EQO CMP X Y EQI

(a)

X0 Y0 1 EQ1 EQO EQI CMP X Y X1 Y1 EQ2 EQO EQI CMP X Y X2 Y2 EQ3 EQO EQI CMP X Y X(N–1) Y(N–1) EQN EQO EQI CMP X Y EQ(N–1)

(b)

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4-bit Comparator 74x85

• Outputs:

– Greater-than output (AGTBOUT) – Less-than output (ALTBOUT) – Equal output (AEQBOUT)

• Cascading inputs:

– AGTBIN, ALTBIN, AEQBIN

• Cascading inputs and the outputs are arranged

in a 1-out-of-3 code, since normally exactly one input and output should be asserted

74x85

2 3 4 10 9 12 11 13 14 15 1

ALTBIN AEQBIN A0 B0 A1 B1 A2 B2 A3 B3 AGTBIN

7 5

ALTBOUT AGTBOUT

6

AEQBOUT

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12-bit Comparator using 74x85s

AGTBOUT = (A>B) + (A=B) · AGTBIN AGTBOUT = (A=B) · AEQBIN AGTBOUT = (A<B) + (A=B) · ALTBIN (A>B) = A3·B3 + (A3B3) · A2·B2 + (A3B3) · (A2B2) · A1· B1 + (A3B3) · (A2B2) · (A1B1) · A0·B0

XNOR

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8-bit Magnitude Comparator

• 74x682

– Does not have cascading inputs (unlike 74x85) – Does not provide a “less than”

• utput

74x682

19 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18

PEQ Q PGT Q P0 Q0 P1 Q1 P2 Q2 P3 Q3 P4 Q4 P5 Q5 P6 Q6 P7 Q7

Compares equality using 4 XNOR gates

PEQQ_L PGTQ_L

Compares if P[7–0] > Q[7–0]

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Arithmetic Conditions from 74x682

• Not-provided conditions

can be implemented as a function of outputs PEQQ_L and PGTQ_L

74x682

19 1

U1 74x00 74x04 74x04 74x08 PNEQ PEQQ PGTQ PGEQ PLEQ PLTQ

1 2 1 1 2 3 3 4 2

U4 U3 U2 U2 PEQQ PGTQ

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