14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University - - PDF document

▶
14 332 231 digital logic design
SMART_READER_LITE
LIVE PREVIEW

14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University - - PDF document

May 23, 2023 496 likes •687 views

14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #12: Multiplexers, Exclusive OR Gates, and Parity Circuits Multiplexers (Data Selectors) A multiplexer (MUX for short)

slide-1
SLIDE 1

1

14:332:231 DIGITAL LOGIC DESIGN

Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013

Lecture #12: Multiplexers, Exclusive OR Gates, and Parity Circuits

2 of 31

Multiplexers (Data Selectors)

  • A multiplexer (MUX for short) is a digital switch:

– it passes (connects) one of its data inputs to the output – the data input selected is a function of a set of control inputs called selection inputs

OUT = S·D0 + S·D1 OUT data inputs control input S 2-to-1 MUX D0 D1

Two alternative forms for a 2:1 MUX truth table D1 1 D0 OUT S

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OUT D0 D1 S

slide-2
SLIDE 2

2

3 of 31

Multiplexers Do Selecting

  • Selecting of data or information is a critical

function in digital systems and computers

  • Circuits that perform selecting have:

– A set of n information inputs Di from which the selection is made – A set of k control (select) lines for making the selection – A single output

k-1 .. 1 0

n ≤ 2k inputs

D0 D1 D2 D3 Dn–1

OUT

1 2 3 . . . n–1

Sk–1 … S1 S0

k select lines

4 of 31

Multiplexer Analogy

(Source: F. Vahid, “Digital Design”, J. Wiley, 2007)

D0 D1 D2 D3 Out

1 2 3 1 0

S1 S0

slide-3
SLIDE 3

3

5 of 31

Example Uses of Multiplexers

  • In computers to select among signals
  • To implement command:

if A=0 then Z=X·Y else Z=XY

  • Trip controller in a car to display mileage, time,

speed, etc.

X Y Z A 1 clock

  • dometer

speed mileage

Display S1

2 1 3 1

S0

Push button

4-to-1 MUX

6 of 31

Multiplexer Structure

  • Switch circuit

equivalent

  • Multiplexer is

unidirectional

s

select SEL Y data

  • utput

b

enable

b

D0

b

D1

b

Dn–1 EN multiplexer n data sources 1D0 1D1 1Dn–1 1Y 2D0 2D1 2Dn–1 2Y bD0 bD1 bDn–1 bY SEL EN

slide-4
SLIDE 4

4

7 of 31

Example: 4-to-1-line Multiplexer

  • Expression for OUT:
  • Circuit implementation: Sum-of-Products

– 4 AND gates (4 product terms) – 2-to-4 line decoder (to generate the minterms)

D3 1 1 D2 1 D1 1 D0 OUT S0 S1 OUT = S1·S0·D0 + S1·S0·D1 + S1·S0·D2 + S1·S0·D3 M0 M1 M2 M3

  • r: OUT = ∑ Mj·Dj

j = 0 2k – 1

8 of 31

Example: 4-to-1-line Multiplexer

  • 2-to-22-line decoder
  • 22 × 2 AND-OR

OUT D0 D1 D2 D3 S0 S1 Decoder M0 M1 M2 M3

slide-5
SLIDE 5

5

9 of 31

General Multiplexer Equation

  • A general logic equation for a multiplexer
  • utput:
  • Logical sum of product terms
  • Variable iY is a particular output bit

(1 ≤ i ≤ b)

  • Mj is a minterm j of the s select inputs

 

  

1 n j j iDj

M EN iY

10 of 31

Gate Level Implementation of MUXs

■ 2:1 MUX ■ 4:1 MUX

positive logic: S D1 OUT D0 negative logic: S D1 OUT D0 OUT S1 S0 D0 D1 D2 D3 OUT S1 S0 D0 D1 D2 D3

slide-6
SLIDE 6

6

11 of 31

Multiplexer Standard Packaging

IC has limited number of pins (16) n·b + b + s + 1 ≤ 16 – 2 in out SEL EN (n+1)·b + log2 n ≤ 13 b n s 1 8 3 (12) 8 input 1 bit 74x151 2 4 2 (12) dual 4 input 2 bit 74x153 4 2 1 (13) quad 2 input 4 bit 74x157

n data inputs b bits per input s select inputs

12 of 31

Truth table of 74x151

  • Truth table for 74x151 8-input, 1-bit multiplexer
  • Only “control” inputs are listed under “Inputs”
  • Outputs specified as 0” or “1”, or a simple logic

function of “data” inputs (e.g., D0 or D0)

D2 D2 1 D3 D3 1 1 D1 D1 1 D4 D4 1 D7 D7 1 1 1 D6 D6 1 1 D5 D5 1 1 D0 D0 1 x x x 1 Y_L Y S0 S1 S2 EN_L Outputs Inputs

slide-7
SLIDE 7

7

13 of 31

74x151 8-input 1-bit Multiplexer

  • 74x151

logic diagram and logic symbol

74x151

7

EN S2 D1 D3 S0 S1 D0 D2 D4 D5 D6 D7

11 10 9 2 4 3 1 15 14 12 13 5 6

Y Y

Y Y_L D5 D0 D6 D7 EN_L

(7) (4) (13) (12) (14) (3) (2) (5) (6)

S0 S1 S2

(11) (10) (9)

D4

(15)

D3

(1)

D1 D2 S0 S0 S1 S1 S2 S2

14 of 31

74x157 2-input 4-bit Multiplexer

  • 74x157

selects between two 4-bit inputs

74x157

15

EN 1D1 2D1 3D1 S 1D0 2D0 3D0 4D0 4D1

1 2 3 11 5 6 10 14 13 7 9

1Y 2Y

4 12

3Y 4Y

slide-8
SLIDE 8

8

15 of 31

74x157 2-input 4-bit Multiplexer

  • 74x157

truth table:

74x157

15

EN 1D1 2D1 3D1 S 1D0 2D0 3D0 4D0 4D1

1 2 3 11 5 6 10 14 13 7 9

1Y 2Y

4 12

3Y 4Y

4D1 3D1 2D1 1D1 1 4D0 3D0 2D0 1D0 x 1 4Y 3Y 2Y 1Y S EN_L Outputs Inputs

16 of 31

Control signals S1 and S0 simultaneously choose

  • ne of D0, D1, D2, D3 and one of D4, D5, D6, D7

Control signal S2 chooses which of the upper or lower mux's output to gate to OUT alternative implementation S0 OUT S2 S1 4:1 mux 2:1 mux 2:1 mux 2:1 mux 2:1 mux D4 D5 D2 D3 D0 D1 D6 D7 8:1 mux

Cascading/Expanding Multiplexers

  • Large multiplexers can be made by cascading

smaller ones

OUT S2 S1 S0 D0 D1 D2 D3 D4 D5 D6 D7 4:1 mux 4:1 mux 2:1 mux 8:1 mux

slide-9
SLIDE 9

9

17 of 31

Cascading/Expanding Multiplexers

  • Combining four 74x151s

to make a 32-to-1 multiplexer

  • 74x138 3-to-8 decoder

used as 2-to-4 decoder for two high-order bits to enable one of 74x151s

18 of 31

Multiplexers as General-purpose Logic

  • A 2n:1 multiplexer can implement any function of n

variables

– with the variables used as control inputs and – the data inputs tied to 0 or 1

  • Example:

F(A,B,C) = M0 + M2 + M6 + M7 = A'·B'·C' + A'·B·C' + A·B·C' + A·B·C = A'·B'·C'·(1) + A'·B'·C·(0) + A'·B·C'·(1) + A'·B·C·(0) + A·B'·C'·(0) + A·B'·C·(0) + A·B·C'·(1) + A·B·C·(1) OUT = A'·B'·C'·I0 + A'·B'·C·I1 + A'·B·C'·I2 + A'·B·C·I3 + A·B'·C'·I4 + A·B'·C·I5 + A·B·C'·I6 + A·B·C·I7

1 1 1 1 1 2 3 4 5 6 7 8:1 MUX S2 S1 S0 A B C F

slide-10
SLIDE 10

10

19 of 31

Multiplexers as General-purpose Logic

  • Generalization:

data inputs can also be tied to variables not just 0’s an 1’s

four possible configurations

  • f truth table

rows can be expressed as a function of In n–1 mux control variables single mux data variable I0 I1 … In–1 In 1 . . . . . . . . 0 In In 1 1 1 1 1 F

20 of 31

Multiplexers as Function Generators

  • We can generate the four possible Z values (0, 1,

Z, Z) and realize the function with half the values

  • Realizing F = ∑X,Y,Z (0,3,5,6) with a 4-input

multiplexer:

74x153 Y

(14) A

1C0 1C2 2G B 1G 1C1 1C3 2C0 2C1 2C2 2C3 X Z

(2) (1) (6) (5) (4) (3) (15) (10) (11) (12) (13) (7) (9) (1) (2)

U1 U2 F unused 1Y 2Y 74x04

1 1 1 7 1 1 1 6 1 1 1 5 1 4 1 1 1 3 1 2 1 1 1 F Z Y X Row Z Z Z Z

I0 I1 … In–1 In

slide-11
SLIDE 11

11

21 of 31

4-variable Function using 8-input Multiplexer

  • Realizing F = ∑N0,N1,N2,N3 (1,2,3,5,7,11,13)

with an 8-input multiplexer:

1 1 1 1 1 1 1 1 N1 1 4 1 1 1 5 1 6 1 1 1 7 1 8 1 1 9 1 10 1 1 1 11 1 1 1 15 1 1 14 1 1 1 1 13 1 1 12 1 1 3 1 2 1 1 1 F N0 N2 N3 Row N0 1 N0 N0 N0 N0 74x151 R

(7)

EN C D1 D3 A B D0 D2 D4 D5 D6 D7 N1

(11) (10) (9) (2) (4) (3) (1) (15) (14) (12) (13) (5) (6)

U1 F Y Y N2 N3 N0 +5V 22 of 31

Demultiplexers

  • Route a single input to one of many
  • utputs, as a function of a set of control

inputs

3

x y0 y1 y2 y3 y4 y5 y6 y7 s[2:0]

1:8 demux

slide-12
SLIDE 12

12

23 of 31

Demultiplexers

  • Demultiplexer function is just the inverse of

multiplexer’s

  • A binary decoder with enable input can be

used as a demultiplexer

24 of 31

Demultiplexer Analogy

  • A MUX driving a bus and a demultiplexer

receiving the bus

SRCA SRCB SRCZ SRC SEL SRCC multiplexer demultiplexer BUS DSTA DSTB DSTZ DEST SEL DSTC MUX SRCA SRCB SRCC SRCZ SRC SEL BUS DMUX DSTA DSTB DSTC DSTZ DEST SEL

slide-13
SLIDE 13

13

25 of 31

Exclusive-OR Gates

  • Exclusive-OR (XOR) gate is a 2-input gate

whose output is “1” if exactly one of its input is “1”

– or: XOR gate produces a “1” output if its inputs are different

  • Exclusive-NOR (XNOR) or Equivalence just
  • pposite—produces output “1” if its inputs are the

same

  • XOR:

X  Y = X·Y + X·Y

  • XNOR:

(X  Y) = X·Y + X·Y

X Y XY X Y (XY)

26 of 31

Exclusive-OR Gates

  • Truth table and gate-level implementation

1 1 1 1 1 1 1 1 (X  Y) (XNOR) X  Y (XOR) Y X

three-level NAND implementation:

X F = X  Y Y

(X·Y) · (X+Y) = (X+Y) · (X+Y) = X·Y + Y·X

AND-OR implementation:

X F = X  Y Y

slide-14
SLIDE 14

14

27 of 31

XOR versus XNOR

(XY) = (X·Y + X·Y) = (X + Y) · (X + Y) = X·X + X·Y + X·Y + Y·Y = X·Y + X·Y X  X

  • ut  out … the circuit XOR = XOR

(X·Y + X·Y) = X·Y + X·Y X  X

  • ut  out … the circuit XNOR = XNOR

X·Y + X·Y X  1 = X·0 + X·1 = X

28 of 31

Equivalent Symbols for XOR/XNOR

  • XOR gates
  • XNOR gates
  • Simple rule:

– Any two signals (inputs or output) of an XOR or XNOR gate may be complemented w/o changing the resulting logic function

X  0 = X X  1 = X

slide-15
SLIDE 15

15

29 of 31

Cascading XOR gates

  • Daisy-chain connection
  • Balanced tree structure

I1 I2 I3 I4 IN ODD ODD I1 I2 I3 I4 IN–1 IN

– Sum modulo 2 – Parity computation N–1 log2(N)

30 of 31

Cascading XOR gates

  • The tree structure is faster than daisy-chain

connection because the gates depth of its treelike structure is log2(N), which is much less than N–1 for a daisy-chain structure

  • Both are called odd-parity circuits because its
  • utput is “1” if an odd number of inputs are “1”

– Used to generate and check parity bits in computer systems

  • Detects any single-bit error
  • Even-parity circuit has odd-parity circuit’s output

inverted—its output is “1” if an even number of its inputs are “1”

slide-16
SLIDE 16

16

31 of 31

Example Parity Computation

F = I1  I2  I3

I1 I2 I3 F

(8) (9) (10)

F = 1 ODD number of “1” in the input

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F I3 I2 I1