14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University - - PDF document

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14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University - - PDF document

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14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #10: Decoders General Decoder Structure A decoder is a logic circuit that converts coded inputs into coded outputs.

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14:332:231 DIGITAL LOGIC DESIGN

Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013

Lecture #10: Decoders

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General Decoder Structure

  • A decoder is a logic circuit that converts

coded inputs into coded outputs.

  • Each input code word produces a different
  • utput code word (there is a one-to-one

mapping between inputs and outputs)

Decoder input code word

  • utput

code word enable inputs m a p

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Decoder Example

  • BCD to seven-segment decoder

– has 4-bit BCD as input code and the “seven-segment code” as its output code

e d c dp Gnd g f a b Vcc d e c g b f a

BCD code

() BCD = binary-coded decimal

a b c d e f g

decoder

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Binary Decoder

  • Accepts a n-bit binary input code and generates a 1-out-
  • f-2n output code
  • Used to activate exactly one of 2n outputs based on n-bit

input value

  • Examples: 2-to-4, 3-to-8, 4-to-16, etc.
  • Note: BCD to seven-segment decoder is NOT

a binary decoder

– Because multiple outputs active simultaneously

  • Binary decoders are

simple and general; can be used to build general decoders (shown later)

Decoder n-bit input binary combination (“code”) index number of an

  • utput line

enable inputs m a p #1 #2n

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Gate Level Implementation of Decoders

S G O0 O1 active-high enable: S G_L O0 O1 active-low enable:

■ 1:2 decoders ■ 2:4 decoders

active-high enable: G O0 O1 O2 O3 S1 S0 active-low enable: G_L O0 O1 O2 O3 S1 S0

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How It Works

■ 2:4 decoder:

– input combination: “00” – output: O0

G O0 O1 O2 O3 S1 S0

– input combination: “10” – output: O2

G O0 O1 O2 O3 S1 S0

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Binary 2-to-4 Decoder

  • Note that the outputs of the decoder

correspond to the minterms: Yi = mi

– e.g., Y0 = I1 · I0 – Y1 = I1 · I0 etc.

1 1 1 1 1 1 1 1 1 1 1 1 x x Y0 Y1 Y2 Y3 I0 I1 EN Outputs Inputs

Note “x” (don’t care) notation.

2-to-4 decoder I0 I1 EN Y0 Y1 Y3 Y2

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MSI 2-to-4 Decoder

■ Input buffering (less load on input circuit) ■ NAND gates (faster operation)

I0 EN

Y0_L

I1

Y1_L Y2_L Y3_L

(1) (4) (5) (6) (7) (2) (3) (* COMPARE TO Wakerly, 4th edition, Figure 6-32(b), page 385 )

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Complete 74x139 Decoder

1A 1G_L 1Y0_L 1B 1Y1_L 1Y2_L 1Y3_L

(1) (4) (5) (6) (7) (2) (3)

(* COMPARE TO 74x138 3-to-8 decoder, described next ) 2A 2G_L 2Y0_L 2B 2Y1_L 2Y2_L 2Y3_L

(15) (12) (11) (10) (9) (14) (13) 74x139 9 10 11 12 7 6 5 4 2 1 1G 1A 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 3 1B 14 15 2G 2A 13 2B

Two 2-to-4 decoders in a single packaging

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74x138: 3-to-8 decoder

  • Commercially available MSI 3-to-8 decoder

– Note that its outputs are active low

» because TTL and CMOS inverting gates are faster than non-inverting gates

74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

■ Logic equations for internal output signals include “enable” signals. ■ Example: Y5 = G1 · G2A · G2B · C · B · A

enable select

  • utputs
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Truth Table for a 3-to-8 Decoder

1 1 1 1 1 1 1 1 1 1 Y5_L 1 1 1 1 1 1 1 x x x 1 x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x x 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Y4_L 1 1 1 1 Y6_L 1 1 1 1 Y7_L x G2B_L x G2A_L 1 1 1 1 G1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x Y0_L Y1_L Y2_L Y3_L A B C Outputs Inputs

■ Because of the inversion bubbles, we have the following relations between internal and external signals G2A = G2A_L Y5 = Y5_L etc.

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3-to-8 Decoder Logic Diagram

G2B_L Y0_L A Y1_L Y2_L Y3_L

(15) (14) (13) (12) (1)

B Y4_L C Y5_L Y6_L Y7_L

(11) (10) (9) (7) (2) (3)

G2A_L G1

(6) (4) (5)

(NOR gate)

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Decoder Cascading

■ Example: Design a 4-to-16 decoder using 74x128s (3-to-8 decoders)

74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 N0 N1 N2 R +5V U1 DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L 74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U2 DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L N3 EN_L

■ Decoders can be cascaded hierarchically to decode larger code words

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More Cascading

5-to-32 decoder

N0 N1 N2 N4 EN2_L 74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U2 DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L 74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U3 DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L 74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U4 DEC16_L DEC17_L DEC18_L DEC19_L DEC20_L DEC21_L DEC22_L DEC23_L 74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 U5 DEC24_L DEC25_L DEC26_L DEC27_L DEC28_L DEC29_L DEC30_L DEC31_L 74x139

1 7 6 5 4 3 2

1G 1A 1B Y0 Y1 Y2 Y3 U1 EN0X7_L EN8X15_L EN16X23_L EN24X31_L EN1 N3 EN3_L

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Decoder Applications

  • Microprocessor memory systems

– Selecting different banks of memory

  • Microprocessor input/output systems

– Selecting different devices

  • Microprocessor instruction decoding

– Enabling different functional units

  • Memory chips

– Enabling different rows of memory depending

  • n address
  • Lots of other applications

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Decoders as General-Purpose Logic

  • n-to-2n decoders can implement any

function of n variables

– with the variables used as control inputs – the appropriate minterms summed to form the function

decoder generates appropriate minterm based on control signals (it “decodes” control signals)

3-to-8 decoder I0 I1 EN Y0 Y1 Y3 Y2 I2 A B C Y4 Y5 Y7 Y6 A·B·C A·B·C A·B·C A·B·C A·B·C A·B·C A·B·C A·B·C

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Decoders as General-Purpose Logic

4-to-16 decoder I0 I1 EN Y0 Y1 Y3 Y2 I2 A B C Y4 Y5 Y7 Y6 A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D I3 D Y8 Y9 Y11 Y10 Y12 Y13 Y15 Y14 A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D F1 F2 F3

■ F1 = A·B·C·D + A·B·C·D + A·B·C·D ■ F2 = A·B·C·D + A·B·C ■ F3 = A + B + C + D

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Customized Decoder Circuit

74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 CS_L RD_L A0 A1 A2 BILL_L JOAN_L PAUL_L ANNA_L FRED_L DAVE_L MARY_L R KATE_L 74x08 74x08 +5V U2 U2 U1

3 2 1 6 5 4

KATE_L 1 1 1 DAVE_L 1 1 FRED_L 1 1 ANNA_L 1 PAUL_L 1 1 JOAN_L 1 MARY_L, KATE_L 1 BILL_L, MARY_L none x x x 1 x none x x x x 1 Output(s) to Assert A0 A1 A2 RD_L CS_L

Truth table Circuit diagram

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Decoder-Based Circuits

Designing a circuit for the logic function F = ∑X,Y,Z (0,2,3,5): (a) Karnaugh map; (b) NAND-based minimal sum-of-products; (c) decoder-based canonical sum.

74x138

6 7 9 10 11 12 13 14 15 3 2 1 4 5

G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Z Y X R +5V U1 F

4 2 1 6

U2

5

74x20 74x00

F

Z 74x00 74x00 74x00 74x10 74x04 74x04

U1 U2 U1 U1 U2 U3 U3

2 1 1 5 3 X Y 4 1 6 2 3 2 6 5 12 13 6 4 4 5 3

(X·Z) (X·Y) (X·Y·Z)

Z X Y

5 7 3 1

1

4 6 2

10 11 01 00

XY X Z Y Z

1 1 1 1

X·Y·Z X·Y X·Z

(a) (b) (c)

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Multiple Decoding w/ a Single Decoder

74x138

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G1 G2A G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Z Y X

G = ∑X,Y,Z (0,1,3) H = ∑X,Y,Z (2,4,5)

R

F = ∑X,Y,Z (3,6,7)

74x08 74x08 +5V U2 U2 U1

5 4 3 6 9 10 11 8

74x08 U2

13 2 1 12