Impact of Gate Placement on RF Degradation in GaN HEMTs Jungwoo Joh - - PowerPoint PPT Presentation

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Impact of Gate Placement on RF Degradation in GaN HEMTs Jungwoo Joh - - PowerPoint PPT Presentation

Sep 25, 2022 187 likes •338 views

Impact of Gate Placement on RF Degradation in GaN HEMTs Jungwoo Joh and Jess A. del Alamo Microsystems Technology Laboratory, MIT Acknowledgements: ARL (DARPA WBGS program) ONR (DRIFT MURI) Accel RF Corporation Motivation RF

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SLIDE 1

Impact of Gate Placement on RF Degradation in GaN HEMTs

Jungwoo Joh and Jesús A. del Alamo Microsystems Technology Laboratory, MIT

Acknowledgements: ARL (DARPA WBGS program) ONR (DRIFT‐MURI) Accel‐RF Corporation

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SLIDE 2

Motivation

  • RF reliability – main concern

in GaN HEMT RF power amplifier

  • Compared to DC stress, little

known about degradation mechanisms under RF stress

– Pout↓, Gain↓ – ID↓, dispersion↑, gm↓, |IG|↑ – RF introduces more degradation than DC [Conway, IRPS 2007; Joh, ROCS 2008; Chini, IEDM 2009; Joh, IEDM 2010]

  • Goal:

– Develop methodology for RF reliability studies – Identify dominant RF degradation mechanisms – Correlate RF and DC reliability

2

Chini, IEDM 2009 Increasing T

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SLIDE 3

Experimental Setup

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DC/Pulsed Characterization

‐ KeithleySources ‐ Agilent B1500A

Windows‐based PC Accel‐RF System Hardware

MIT RF/DC Characterization Suite ‐ DC FOMs ‐ Current collapse

DUT

Switching Matrix RF/DC Units Accel‐RF Software ‐ RF measurement ‐Temperature control ‐ Stressing

Tbase

Heater

Accel‐RF system augmented with:

  • external instrumentation for DC/pulsed

characterization

  • software to control external

instrumentation and extract DC and RF FOMs Accel‐RF AARTS RF10000‐4/S system:

  • two 2‐4 GHz channels
  • two 7‐12 GHz channels
  • Max Pin=30 dBm
  • Tbase=50‐200 °C
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SLIDE 4

RF Experiment Flowchart: Conventional Approach

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Limitations:

  • Bias point shifts during stress
  • Limited RF characterization
  • No DC characterization
  • No trap characterization
  • If examining different RF

conditions, RF characterization confusing START RF Stress Pout, PAE, Gain, IDQ, IGQ END

Tstress

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SLIDE 5

RF Experiment Flowchart: Improved Approach

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  • Short characterization:

– Every few minutes at Tbase=50 °C – DC FOMs: IDmax, RS, RD, VT, IGoff, … – RF FOMs @ VDS=28 V & IDQ=100 mA/mm

  • Saturated conditions (Pin=23 dBm):

Pout,sat, Gsat, PAE

  • Linear conditions (Pin=10 dBm): Glin
  • Full Characterization:

– After key events at room temperature – Full DC I‐V sweep – Current collapse (after 1” VDS=0, VGS=‐ 10 V pulse) – Full RF power sweep @ VDS=28 V, IDQ=100 mA/mm

  • Detrapping: Tbase=100°C for 30 mins

Full Characterization (DC, RF, CC)

START RF (DC) Stress

Short Characterization (DC, RF) Key Event?

END: detrapping + Full characterization

YES

Detrapping

NO

Tstress RT Tbase=50°C

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SLIDE 6

5 10 15 20 25 2 4 6 8 10 12 14 10 15 20 25 30

PAE (%) Gain (dB) Pin (dBm) PAE Gain

Pin Step‐Stress: Centered Gate

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  • Motivation:

– higher Pin  larger V waveform at output

  • MMIC:

– single‐stage internally‐matched – 4x100 μm GaN HEMT – Gate placed at the center btw S & D

  • Step Pin stress:

– VDS = 40 V, IDQ = 100 mA/mm – Pin = 0 (DC), 1, 20‐27 dBm – 300 min stress at each step – Tstress=50 °C

VDS=40 V, IDQ=100 mA/mm

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SLIDE 7

10 20 30 40 50 60 29 30 31 32 33 Time (hr) Pout (dBm) 10 20 30 40 50 60 5 10 15 20 25 30 Time (hr) Pin (dBm)

Characterization during RF Stress

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  • RF FOMs changing because Pin changing
  • Degradation apparent but not easily quantifiable

Pout Gain

Pin Pout IDQ PAE

Full Characterization (DC, RF, CC)

START RF (DC) Stress

Short Characterization (DC, RF) Key Event?

END: detrapping + Full characterization

YES

Detrapping

NO

Tstress RT Tbase=50°C

DC DC

20 40 60

  • 100

100 200 300 400 Time (hr) IDQ (mA/mm) 10 20 30 40 50 60 5 10 15 20 25 30 Time (hr) PAE (%)

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SLIDE 8

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 0.8 0.9 1 1.1 1.2 1000 2000 3000 |IGoff| (mA/mm) IDmax/IDmax(0), R/R(0) Time (min)

IDmax RS RD IGoff

DC|Pin=1 20 21 22 23 24 25 26 27 dBm

DC FOM during Short Characterization

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  • Little degradation under DC and low Pin
  • Beyond Pin=20 dBm:

— RF induces degradation of IDmax and RD — Sharp degradation in IGoff Tbase=50°C

Full Characterization (DC, RF, CC)

START RF (DC) Stress

Short Characterization (DC, RF) Key Event?

END: detrapping + Full characterization

YES

Detrapping

NO

Tstress RT Tbase=50°C

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SLIDE 9

29 30 31 32 33 1 2 3 4 5 6 7 8 9 ‐10 10 20 30 Saturated Pout (dBm) Permanent IDmax Degradation (%) Current Collapse (%) Stress Input Power Pin (dBm)

Initial DC RF

Pout  Current Collapse Δ|IDmax|

Tbase=RT

DC/RF/CC Full Characterization

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  • Similar critical behavior. Beyond Pin=20 dBm:

― Sharp Pout degradation ― permanent degradation of IDmax ― Evidence of new traps created (increased CC)

Full Characterization (DC, RF, CC)

START RF (DC) Stress

Short Characterization (DC, RF) Key Event?

END: detrapping + Full characterization

YES

Detrapping

NO

Tstress RT Tbase=50°C 100 °C

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SLIDE 10

Structural Degradation (Planar View)

  • Pit formation along the drain side of gate edge
  • Same degradation mechanism as in DC high field OFF‐state

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SEM AFM

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SLIDE 11

Correlation between DC and RF FOM

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VDS=28 V, Tbase=50 C

  • Good correlation between Pout and IDmax degradation

ΔPout=1 dB ↔ ΔIDmax =9%

30 30.5 31 31.5 32 32.5 650 700 750 800 850 Pout (dBm) IDmax (mA/mm) Short characterization @ 50 °C

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SLIDE 12

Step Pin Stress: Offset Gate

1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 0.5 1 1.5 2 2.5 3 300 600 900 1200 |IGoff| (mA/mm) IDmax/IDmax(0), R/R(0) Time (min)

IDmax RS RD IGoff  Inner loop (50°C) DC RF Pin=20 23 26 dBm

13 13.5 14 14.5 15 30 30.5 31 31.5 32 32.5 300 600 900 1200 Small Signal Gain Glin (dB) Saturated Pout (dBm) Time (min)

Gain Pout

DC RF Pin=20 23 26 dBm Inner loop (50°C)

RF FOM DC FOM Joh, IEDM 2010

  • More degradation under RF stress @ high Pin
  • No IGoff degradation (high Vcrit)
  • Degradation in IDmax and RS, not in RD
  • No structural degradation

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SLIDE 13

Pulsed Stress: High‐power State

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  • High‐power stress not accessible in DC  pulsed stress
  • Pulsed stress reproduces large RS degradation in offset gate
  • No RS degradation in centered gate

1 1.1 1.2 1.3 1.4 20 40 60 80 Normalized RS Stress VDS (V) Offset gate Centered gate 100 pulses, 500 us, 0.05% duty IDpulse=950 mA/mm ID VDS High-power

RF Load Line

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SLIDE 14

Summary

  • Developed new RF reliability testing

methodology

  • Critical behavior in RF stress on centered gate:

– Pin↑  Pout↓ (>> DC stress) – IDmax↓, current collapse↑, IGoff ↑ – Good correlation between DC and RF FOMs – Structural degradation on drain‐side gate edge – Same degradation mechanism under high‐voltage OFF‐state DC stress

  • Offset gate:

– Different degradation mechanism is present – Significant RS degradation

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