CHAPTER IV GATE DESIGN R.M. Dansereau; v.1.0 GATE NETWORKS INTRO. - - PowerPoint PPT Presentation

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CHAPTER IV GATE DESIGN R.M. Dansereau; v.1.0 GATE NETWORKS INTRO. - - PowerPoint PPT Presentation

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INTRO. TO COMP. ENG. CHAPTER IV CHAPTER IV-1 GATE DESIGN CHAPTER IV GATE DESIGN R.M. Dansereau; v.1.0 GATE NETWORKS INTRO. TO COMP. ENG. GATE NETWORKS CHAPTER IV-2 INTRODUCTION GATE DESIGN Gate network consists of Gates

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SLIDE 1

R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-1 GATE DESIGN

  • CHAPTER IV

CHAPTER IV GATE DESIGN

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SLIDE 2

R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-2

GATE NETWORKS

INTRODUCTION

GATE DESIGN

  • GATE NETWORKS
  • Gate network consists of
  • Gates
  • External inputs and outputs
  • Connections
  • Gate inputs
  • Only one connection to input is allowed (unless tri-state device is used)
  • Connected to constant value (0 or 1)
  • Connected to an external input
  • Connected to a gate output
  • Gate outputs
  • Output load should not be greater then the fanout factor for the gate and

technology being used.

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-3

GATE NETWORKS

VALID/INVALID NETWORKS

GATE DESIGN

  • GATE NETWORKS
  • INTRODUCTION

G1 G3 G2 Valid or Invalid? G1 G3 G2 Valid or Invalid? G1 G3 G2 Valid or Invalid? G1 G3 G2 Valid or Invalid? G6

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-4

LOGIC GATES

NON-INVERTING OPERATORS

GATE DESIGN

  • GATE NETWORKS
  • INTRODUCTION
  • VALID/INVALID NET.

A B 1 1 1 1 1 A B F AND F A B 1 1 1 1 1 1 1 F A B 1 1 1 1 1 1 F A B F A B F A 1 1 F OR BUFFER XOR A F F AB = F A B + = F A = F AB AB + A B ⊕ = = 6 transistors 6 transistors 8 transistors

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-5

LOGIC GATES

INVERTING OPERATORS

GATE DESIGN

  • GATE NETWORKS
  • LOGIC GATES
  • NON-INVERTING OPER.

A B 1 1 1 1 1 1 1 A B F NAND F A B 1 1 1 1 1 F A B 1 1 1 1 1 1 F A B F A B F A 1 1 F NOR NOT XNOR A F F AB = F A B + = F A = F AB AB + A B ⊕ = = 4 transistors 4 transistors 2 transistors 8 transistors

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-6

LOGIC GATES

INVERTERS

GATE DESIGN

  • GATE NETWORKS
  • LOGIC GATES
  • NON-INVERTING OPER.
  • INVERTING OPERATOR
  • Inverters can also be implemented with a NAND or with a NOR gate.

A 1 1 F NOT A F F A = A A 1 1 1 A F NAND F F AA A = = A A 1 1 1 F F NOR F A A + A = = A A 1 1 1 1 1 A F NAND F F A 1 ⋅ A = = 1

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-7

LOGIC NETWORKS

FROM BOOLEAN FUNCTIONS

GATE DESIGN

  • LOGIC GATES
  • NON-INVERTING OPER.
  • INVERTING OPERATORS
  • INVERTERS
  • Implement the following Boolean function using logic gates
  • Possible solution:
  • transistors for CMOS technology.

F A BC + ( )D ( ) C DE + + = A B C D F E 3 6AND × 3 6OR × 3 2NOT × + + 42 =

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-8

LOGIC NETWORKS

USING SPECIFIC GATES

GATE DESIGN

  • LOGIC GATES
  • LOGIC NETWORKS
  • FROM BOOL. FUNCTIONS
  • Because of various implementation reasons, it may be desired to use only

specific sorts of logic gates in an implementation.

  • For instance, many CMOS implementations use only NAND gates.

Some implementations use only NOR gates.

  • This can be done in a number of manners. One is to rework the Boolean

functions so that only the specific gates desired are used.

  • May reduce the physical number of transistors required if the appropriate

types of gates are used.

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-9

LOGIC NETWORKS

EXAMPLE USING NAND GATES

GATE DESIGN

  • LOGIC GATES
  • LOGIC NETWORKS
  • FROM BOOL. FUNCTIONS
  • USING SPECIFIC GATES
  • Implement the following Boolean function using NAND gates
  • This Boolean function can be expressed as

F A BC + ( )D ( ) C DE + + = F ABCDCDE A′ BC′ ( )′ ( )′D ( ) C′ ( ) DE ( )′ ( )′′ = = A B C D E F 6 4NAND-2 × 8NAND-4 + 32 = 3 4NAND-2 × 8NAND-4 3 2NOT × + + 26 = transistors transistors How to implement 4-input NAND?

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SLIDE 10

R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-10

MIXED LOGIC

INTRODUCTION

GATE DESIGN

  • LOGIC NETWORKS
  • FROM BOOL. FUNCTIONS
  • USING SPECIFIC GATES
  • EXAMPLE USING NAND
  • Mixed logic is one approach that makes it easier to redesign a logic

network to use desired types of gates.

  • Mixed logic is also self-documenting
  • This means that you can see what the original designer started with and

see how the logic network was changed for the implementation.

  • The idea behind mixed logic is to diagram out the logic network from the

Boolean equations given, and then make small changes to the logic network to achieve desired results for implementation.

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-11

MIXED LOGIC

DEMORGAN’S SQUARE

GATE DESIGN

  • LOGIC NETWORKS
  • MIXED LOGIC
  • INTRODUCTION
  • DeMorgan’s Square

A B 1 1 1 1 1 1 1

NAND

F A B 1 1 1 1 1 F

NOR

A B 1 1 1 1 1

AND

F A B 1 1 1 1 1 1 1 F

OR

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-12

MIXED LOGIC

MIXED LOGIC PROCEDURE

GATE DESIGN

  • LOGIC NETWORKS
  • MIXED LOGIC
  • INTRODUCTION
  • DEMORGAN’S SQUARE
  • The procedure for performing mixed logic conversions is as follows:
  • Draw the logic network for the given Boolean equation.
  • Use only AND and OR gates.
  • Replace all complements with a bar (no bubbles or inverters yet!)
  • Once the initial Boolean equation is drawn with AND gates, OR gates

and bars, the self-documenting redesign begins:

  • Add complement bubbles and NOT gates within the network to

appropriately convert logic gates to desired gate sets.

  • The rules in adding complement bubbles and NOT gates
  • All bubbles must cancel each other out
  • Exactly one and only one bubble needed on each bar
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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-13

MIXED LOGIC

EXAMPLE #1 (1)

GATE DESIGN

  • MIXED LOGIC
  • INTRODUCTION
  • DEMORGAN’S SQUARE
  • MIXED LOGIC PROC.
  • Implement the following Boolean function using NAND gates and then also

using NOR gates.

  • Solution: Start by drawing the logic network for the Boolean function with

the complements as bars.

  • This completes the information needed to get back original equation.

F AB CD + = A B C D F

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-14

MIXED LOGIC

EXAMPLE #1 (2)

GATE DESIGN

  • MIXED LOGIC
  • DEMORGAN’S SQUARE
  • PROCEDURE
  • EXAMPLE #1

continued... using NAND gates

  • This logic network now only uses NAND gates and inverters.
  • This results in the following Boolean function, as obtained previously

A B C D F F A B C D E , , , , ( ) ABCD =

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-15

MIXED LOGIC

EXAMPLE #1 (3)

GATE DESIGN

  • MIXED LOGIC
  • DEMORGAN’S SQUARE
  • PROCEDURE
  • EXAMPLE #1

continued... using NOR gates

  • This logic network now only uses NOR gates and inverters.
  • This results in the following Boolean function, as obtained previously

A B C D F F A B C D E , , , , ( ) A B + C D + + =

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-16

MIXED LOGIC

EXAMPLE #2 (1)

GATE DESIGN

  • MIXED LOGIC
  • DEMORGAN’S SQUARE
  • PROCEDURE
  • EXAMPLE #1
  • Implement the following Boolean function using NAND gates
  • Solution: Start by drawing the logic network for the Boolean function with

the complements as bars. F A BC + ( )D ( ) C DE + + = A B C D F E

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R.M. Dansereau; v.1.0

  • INTRO. TO COMP. ENG.

CHAPTER IV-17

MIXED LOGIC

EXAMPLE #2 (2)

GATE DESIGN

  • MIXED LOGIC
  • PROCEDURE
  • EXAMPLE #1
  • EXAMPLE #2

continued...

  • This logic network now only uses NAND gates and inverters.
  • This results in the following Boolean function, as obtained previously

A B C D F E F A B C D E , , , , ( ) ABCDCDE ABCDCDE = =