INTRO. TO COMP. ENG. •CHAPTER IV CHAPTER IV-1 GATE DESIGN CHAPTER IV GATE DESIGN R.M. Dansereau; v.1.0
GATE NETWORKS INTRO. TO COMP. ENG. •GATE NETWORKS CHAPTER IV-2 INTRODUCTION GATE DESIGN • Gate network consists of • Gates • External inputs and outputs • Connections • Gate inputs • Only one connection to input is allowed (unless tri-state device is used) • Connected to constant value ( 0 or 1 ) • Connected to an external input • Connected to a gate output • Gate outputs • Output load should not be greater then the fanout factor for the gate and technology being used. R.M. Dansereau; v.1.0
GATE NETWORKS INTRO. TO COMP. ENG. •GATE NETWORKS -INTRODUCTION CHAPTER IV-3 VALID/INVALID NETWORKS GATE DESIGN G 1 G 2 G 1 G 3 G 3 G 2 Valid or Invalid? G 6 Valid or Invalid? G 1 G 3 G 1 G 3 G 2 G 2 Valid or Invalid? Valid or Invalid? R.M. Dansereau; v.1.0
LOGIC GATES INTRO. TO COMP. ENG. •GATE NETWORKS -INTRODUCTION CHAPTER IV-4 -VALID/INVALID NET. NON-INVERTING OPERATORS GATE DESIGN A B F A B F AND OR 0 0 0 0 0 0 0 1 0 0 1 1 A A F F 1 0 0 1 0 1 B B 1 1 1 1 1 1 F AB F A B = = + 6 transistors 6 transistors A B F XOR BUFFER A F 0 0 0 0 0 0 1 1 A F A F 1 1 1 0 1 B 1 1 0 ⊕ F A F AB AB A B = = + = 8 transistors R.M. Dansereau; v.1.0
LOGIC GATES INTRO. TO COMP. ENG. •GATE NETWORKS •LOGIC GATES CHAPTER IV-5 -NON-INVERTING OPER. INVERTING OPERATORS GATE DESIGN A B F A B F NAND NOR 0 0 1 0 0 1 0 0 1 1 1 0 A A F F 1 0 1 1 0 0 B B 1 1 0 1 1 0 F AB F A B = = + 4 transistors 4 transistors A B F XNOR NOT A F 0 0 1 0 1 0 1 0 A F A F 1 0 1 0 0 B 1 1 1 ⊕ F A F AB AB A B = = + = 2 transistors 8 transistors R.M. Dansereau; v.1.0
LOGIC GATES INTRO. TO COMP. ENG. •GATE NETWORKS •LOGIC GATES CHAPTER IV-6 -NON-INVERTING OPER. INVERTERS GATE DESIGN -INVERTING OPERATOR • Inverters can also be implemented with a NAND or with a NOR gate. NAND NOT A F A A F A 0 1 A F 0 0 1 F 1 1 0 1 0 F A = F AA A = = NAND NOR A 1 F A A F A F F 0 1 1 A 0 0 1 1 1 1 0 1 1 0 ⋅ F A 1 A F A A A = = = + = R.M. Dansereau; v.1.0
LOGIC NETWORKS INTRO. TO COMP. ENG. •LOGIC GATES -NON-INVERTING OPER. CHAPTER IV-7 -INVERTING OPERATORS FROM BOOLEAN FUNCTIONS GATE DESIGN -INVERTERS • Implement the following Boolean function using logic gates ( ( ) D ) F A BC C DE = + + + • Possible solution: A B C D F E × × × • 3 6 AND 3 6 OR 3 2 NOT 42 transistors for CMOS technology. + + = R.M. Dansereau; v.1.0
LOGIC NETWORKS INTRO. TO COMP. ENG. •LOGIC GATES •LOGIC NETWORKS CHAPTER IV-8 -FROM BOOL. FUNCTIONS USING SPECIFIC GATES GATE DESIGN • Because of various implementation reasons, it may be desired to use only specific sorts of logic gates in an implementation. • For instance, many CMOS implementations use only NAND gates. Some implementations use only NOR gates. • This can be done in a number of manners. One is to rework the Boolean functions so that only the specific gates desired are used. • May reduce the physical number of transistors required if the appropriate types of gates are used. R.M. Dansereau; v.1.0
LOGIC NETWORKS INTRO. TO COMP. ENG. •LOGIC GATES •LOGIC NETWORKS CHAPTER IV-9 -FROM BOOL. FUNCTIONS EXAMPLE USING NAND GATES GATE DESIGN -USING SPECIFIC GATES • Implement the following Boolean function using NAND gates ( ( ) D ) F A BC C DE = + + + • This Boolean function can be expressed as ( ( ( A ′ BC ′ ( )′ )′ D ) C ′ ( ) DE ( )′ )′′ F ABCDCDE = = A How to implement 4-input NAND? B C F × D 6 4 NAND-2 8 NAND-4 32 transistors + = E × × 3 4 NAND-2 8 NAND-4 3 2 NOT 26 transistors + + = R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •LOGIC NETWORKS -FROM BOOL. FUNCTIONS CHAPTER IV-10 -USING SPECIFIC GATES INTRODUCTION GATE DESIGN -EXAMPLE USING NAND • Mixed logic is one approach that makes it easier to redesign a logic network to use desired types of gates . • Mixed logic is also self-documenting • This means that you can see what the original designer started with and see how the logic network was changed for the implementation. • The idea behind mixed logic is to diagram out the logic network from the Boolean equations given, and then make small changes to the logic network to achieve desired results for implementation. R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •LOGIC NETWORKS •MIXED LOGIC CHAPTER IV-11 -INTRODUCTION DEMORGAN’S SQUARE GATE DESIGN • DeMorgan’s Square AND OR A B F A B F 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 1 NAND NOR A B F A B F 0 0 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 0 R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •LOGIC NETWORKS •MIXED LOGIC CHAPTER IV-12 -INTRODUCTION MIXED LOGIC PROCEDURE GATE DESIGN -DEMORGAN’S SQUARE • The procedure for performing mixed logic conversions is as follows: • Draw the logic network for the given Boolean equation. • Use only AND and OR gates. • Replace all complements with a bar (no bubbles or inverters yet!) • Once the initial Boolean equation is drawn with AND gates, OR gates and bars, the self-documenting redesign begins: • Add complement bubbles and NOT gates within the network to appropriately convert logic gates to desired gate sets. • The rules in adding complement bubbles and NOT gates • All bubbles must cancel each other out • Exactly one and only one bubble needed on each bar R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •MIXED LOGIC -INTRODUCTION CHAPTER IV-13 -DEMORGAN’S SQUARE EXAMPLE #1 (1) GATE DESIGN -MIXED LOGIC PROC. • Implement the following Boolean function using NAND gates and then also using NOR gates. F AB CD = + • Solution: Start by drawing the logic network for the Boolean function with the complements as bars. A B F C D • This completes the information needed to get back original equation. R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •MIXED LOGIC -DEMORGAN’S SQUARE CHAPTER IV-14 -PROCEDURE EXAMPLE #1 (2) GATE DESIGN -EXAMPLE #1 continued... using NAND gates A B F C D • This logic network now only uses NAND gates and inverters. • This results in the following Boolean function, as obtained previously ( , , , , ) F A B C D E ABCD = R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •MIXED LOGIC -DEMORGAN’S SQUARE CHAPTER IV-15 -PROCEDURE EXAMPLE #1 (3) GATE DESIGN -EXAMPLE #1 continued... using NOR gates A B F C D • This logic network now only uses NOR gates and inverters. • This results in the following Boolean function, as obtained previously ( , , , , ) F A B C D E A B C D = + + + R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •MIXED LOGIC -DEMORGAN’S SQUARE CHAPTER IV-16 -PROCEDURE EXAMPLE #2 (1) GATE DESIGN -EXAMPLE #1 • Implement the following Boolean function using NAND gates ( ( ) D ) F A BC C DE = + + + • Solution: Start by drawing the logic network for the Boolean function with the complements as bars. A B C D F E R.M. Dansereau; v.1.0
MIXED LOGIC INTRO. TO COMP. ENG. •MIXED LOGIC -PROCEDURE CHAPTER IV-17 -EXAMPLE #1 EXAMPLE #2 (2) GATE DESIGN -EXAMPLE #2 continued... A B C D F E • This logic network now only uses NAND gates and inverters. • This results in the following Boolean function, as obtained previously ( , , , , ) F A B C D E ABCDCDE ABCDCDE = = R.M. Dansereau; v.1.0
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