[PPT] - Design for Testability (DFT) Sh Sh Shaahin Hessabi Shaahin PowerPoint Presentation

SLIDE 1

Testability: Lecture 23

Design for Testability (DFT)

Sh hi H bi Sh hi H bi Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology Adapted, with modifications, from lecture notes prepared by the Adapted, with modifications, from lecture notes prepared by the p , , p p y p , , p p y book authors book authors

Slide 1 of 43

SLIDE 2

Outline

Iterative Logic Arrays

Ad

Ad-

hoc DFT methods

hoc DFT methods

Scan design

Scan design g

Design rules

Design rules Scan register Scan register

Scan register

Scan flip

Scan flip-

flops

flops

Scan test sequences

Overheads

Scan design system

Slide 2 of 43 Sharif University of Technology Testability: Lecture 23

SLIDE 3

Iterative Logic Arrays (ILAs)

Some circuits are easy to test, for example, ILAs Definition: An ILA is a k-dimensional array-like circuit composed

e

s a

d e s o a a ay e c cu co posed

f identical cells with uniform interconnections

Array circuits can be tested for powerful fault models using

relatively few tests relatively few tests

Examples:

Arithmetic circuits Arithmetic circuits Ripple-carry adders Array multipliers Array multipliers Bit-sliced processors Random-access memories: RAMs, ROMs Random access memories: RAMs, ROMs ILA models of sequential circuits

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Example 1: Ripple-Carry Adder

1D array composed of full-adder cells

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Example 1: Ripple-Carry Adder (cont’d)

Assume the cell fault (CF) model, which implies that all

i l l i f lt i ll li ti ill b d t t d

We must apply eight

single logic faults in all realizations will be detected.

patterns to every cell and

bserve the responses.

Six of the 8 patterns can be

applied simultaneously to all cells; e.g., AiBiCi = 000

Faults in FAi can be observed via Si or Ci+1

i i i+1

Two of the 8 patterns cannot be applied simultaneously to

all cells, namely AiBiCi = 001 and 110, because Cin ≠ Cout

Slide 5 of 43 Sharif University of Technology Testability: Lecture 23

y

i i i in

ut

SLIDE 6

Example 1: Ripple-Carry Adder (cont’d) p pp y ( )

The patterns AiBiCi = 001 and 110

b li d i l l can be applied simultaneously to alternating cells All CF f lt i bit RC dd

All CF faults in an n-bit RC adder

can be detected by 8 tests, independent of the array size n.

The property of an n-cell ILA that all (cell) faults can be

d d b b f i ll d independent of the array size n. detected by a constant number test patterns for any n is called C-testability

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Example 2: Gate Array

This is an ILA realization of a k

This is an ILA realization of a k-

input AND function,

input AND function,

k k = = 1 1, ,2 2, ,3 3, ,…

Question 1: Is an AND array C

: Is an AND array C-

testable?

testable?

Question

Question2 2: What if the AND function is replaced by : What if the AND function is replaced by XOR? XOR?

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Design for Testability (DFT)

Test generation algorithms for logic circuits are complex

Test generation algorithms for logic circuits are complex (NP complete) (NP complete) (NP complete) (NP complete)

Circuits containing, say,

Circuits containing, say, 10 106 gates or gates or 10 102 flip flip-

flops, may

flops, may be too large for ATPG tools be too large for ATPG tools be too large for ATPG tools be too large for ATPG tools

Heuristic methods are used for testing complex circuits

Heuristic methods are used for testing complex circuits such as microprocessors RAMs etc such as microprocessors RAMs etc such as microprocessors, RAMs, etc. such as microprocessors, RAMs, etc.

Fault coverage of such methods can be low and hard to

Fault coverage of such methods can be low and hard to dete mine dete mine determine determine

To ensure high levels of testability, design for testability

To ensure high levels of testability, design for testability (DFT) i ft ti l (DFT) i ft ti l (DFT) is often essential (DFT) is often essential

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Testability Goals

1. 1.

Maximize fault coverage Maximize fault coverage

2

Minimize test application time Minimize test application time

2. 2.

Minimize test application time Minimize test application time

3. 3.

Minimize test data size Minimize test data size

4. 4.

Minimize test generation effort Minimize test generation effort

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Definition

Design for testability

Design for testability (DFT) refers to those design (DFT) refers to those design techniques that make test generation and test techniques that make test generation and test techniques that make test generation and test techniques that make test generation and test application cost application cost-

effective.

effective.

DFT methods for digital circuits:

Ad

Ad-

hoc methods

hoc methods

Structured methods:

Structured methods:

Scan

Scan P i l S P i l S

Partial Scan

Built

Built-

in self

in self-

test

test (BIST) (BIST)

Boundary scan

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DFT

In general, DFT deals with ways for improving

In general, DFT deals with ways for improving controllability and observability controllability and observability controllability and observability controllability and observability

Costs associated with DFT:

Pins Area/Yield Area/Yield Performance Design time Slide 11 of 43 Sharif University of Technology Testability: Lecture 23

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Objections to DFT j

Short-sighted view of management (schedule and costs)

g g ( )

Life-cycle cost ignored by development

management/contractors/buyers g / / y

Area/functionality/performance myths Lack of knowledge by design engineers Lack of knowledge by design engineers Testing is someone else’s problem

L k f t l t t DFT (thi i i i )

Lack of tools to support DFT (this is improving….)

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Ad-Hoc DFT Methods

Good design practices learnt through experience are

Good design practices learnt through experience are used as guidelines: used as guidelines: used as guidelines: used as guidelines:

Avoid asynchronous (

Avoid asynchronous (unclocked unclocked) feedback. ) feedback. ( (⇒oscillation)

scillation)

Make flip

Make flip-

flops

flops initializable

initializable. (

. (clear clear or

r preset

preset) )

Avoid redundant gates. Avoid large fan

Avoid redundant gates. Avoid large fan-

in gates.

in gates. (controllability, observability) (controllability, observability)

Provide test control for difficult

Provide test control for difficult-to to-control signals. control signals.

Provide test control for difficult

Provide test control for difficult to to control signals. control signals.

Avoid gated clocks.

Avoid gated clocks. C id ATE i t ( C id ATE i t (t i t t t i t t t ) t )

Consider ATE requirements (

Consider ATE requirements (tristates tristates, etc.) , etc.)

Design reviews conducted by experts or design

Design reviews conducted by experts or design diti t l diti t l

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auditing tools. auditing tools.

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Disadvantages of Ad-Hoc DFT Methods

Circuits are too large for manual inspection.

Circuits are too large for manual inspection.

Experts and tools not always available.

Experts and tools not always available.

Test generation is often manual with no guarantee of

Test generation is often manual with no guarantee of g a o

a ua
gua a
g

a o

a ua
gua a
high fault coverage.

high fault coverage.

Design iterations may be necessary.

Design iterations may be necessary. Design iterations may be necessary. Design iterations may be necessary.

Use of ad

se of ad-

hoc DFT is usually discouraged for large

hoc DFT is usually discouraged for large circuits. circuits. circuits. circuits.

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Ad Hoc Design Rules

Partitioning

Insert control/observation points (

Insert control/observation points (test points test points), e.g., a ), e.g., a reset line for initialization reset line for initialization

Avoid redundancy

Improve circuit structure, e.g., break global feedback

Improve circuit structure, e.g., break global feedback during testing during testing

Provide clock access during testing

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Partitioning (Divide and Conquer)

Physically divide the system into multiple chips or boards.

Physically divide the system into multiple chips or boards. y y y p p y y y p p

On board

On board-

level systems, use jumper wires to divide

level systems, use jumper wires to divide subunits. subunits. subunits. subunits.

Has major performance penalties.

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Partitioning using Degating

Degating: another technique for separating modules on

Degating: another technique for separating modules on f chip/board with lower performance penalties. chip/board with lower performance penalties.

clock degating

module partitioning

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Test Point Insertion

Make hard

Make hard-

to

to-

control internal signals controllable via extra

control internal signals controllable via extra primary inputs and logic (CP = control points) primary inputs and logic (CP = control points) primary inputs and logic (CP = control points) primary inputs and logic (CP = control points)

Make hard

Make hard-

to

to-

observe internal signals observable via extra
bserve internal signals observable via extra

primary outputs and logic (OP = observation points) primary outputs and logic (OP = observation points) primary outputs and logic (OP = observation points) primary outputs and logic (OP = observation points)

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Test Point Insertion (cont’d)

Control Control-

Point Sites

Point Sites

Clock lines

Global reset lines

Inputs of state

Inputs of state-

control devices

control devices

Lines of high fan

Lines of high fan-

out (fan
ut (fan-
out stems)
ut stems)

Control (especially

Control (especially tristate tristate control) lines of buses control) lines of buses

All bus lines in bus

All bus lines in bus structured designs structured designs

All bus lines in bus

All bus lines in bus-structured designs structured designs

Control inputs to (embedded) RAMS and ROMs

Some enable/hold/select control lines

Lines identified by testability measuring programs as having low

Lines identified by testability measuring programs as having low controllability controllability

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Test Point Insertion (cont’d)

Observation Observation-

Point Sites

Point Sites

“Buried

Buried” (not directly accessible) control/status lines (not directly accessible) control/status lines O t t f t t O t t f t t t l d i t l d i

Outputs of state

Outputs of state-

control devices

control devices

Lines of high fan

Lines of high fan-

out (fan
ut (fan-
out stems)
ut stems)

Outputs of

Outputs of high fan high fan-in in circuits, e.g. parity generators circuits, e.g. parity generators p g , g p y g , g p y g

Logically redundant nodes

Global feedback paths

Output lines in bus

Output lines in bus-structured designs structured designs

Output lines in bus

Output lines in bus-structured designs structured designs

Lines identified by testability measuring programs as having low

bservability
bservability

M i Li it ti M i Li it ti Main Limitation Main Limitation

Availability of (spare) input/output terminals

Add MUX’s to reduce number of I/O pins Add MUX s to reduce number of I/O pins Serially shifts control point values

Long testing time

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Test Point Insertion (cont’d)

Memory Control/Observation Memory Control/Observation

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DFT: Circuit Restructuring

Example: Counter Design

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DFT: Timing Control

Avoid asynchronous timing

Make clocks observable and controllable during testing

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Design Rule Summary

Partition large hard

Partition large hard-

to

to-

test circuits into small testable

test circuits into small testable components components

Design controllable (e.g.

Design controllable (e.g. initializable initializable) and observable units ) and observable units with careful selection of control/test points with careful selection of control/test points

Allow global feedback paths to be opened/closed

Avoid redundancy, or allow it to be overridden during

Avoid redundancy, or allow it to be overridden during testing testing

Avoid asynchronous circuits, provide access to clock signals

Conclusions Conclusions

Often ad hoc design modification is too late to significantly

Often ad hoc design modification is too late to significantly improve a circuit's testability improve a circuit's testability D l i l h f h d i D l i l h f h d i

Develop a systematic test plan at the start of the design

Develop a systematic test plan at the start of the design process process

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Scan Design

Circuit is designed using pre

Circuit is designed using pre-

specified design rules.

specified design rules.

Test structure (hardware) is added to the verified design:

Add a

Add a test control test control (TC) primary input. (TC) primary input.

Replace flip

Replace flip-

flops by

flops by scan flip scan flip-

flops

flops (SFF) and connect to form one or (SFF) and connect to form one or more shift registers in the test mode. more shift registers in the test mode. g

Make input/output of each scan shift register controllable/observable

Make input/output of each scan shift register controllable/observable from PI/PO from PI/PO from PI/PO. from PI/PO.

Use combinational ATPG to obtain tests for all testable

Use combinational ATPG to obtain tests for all testable faults in the combinational logic faults in the combinational logic faults in the combinational logic. faults in the combinational logic.

Add shift register tests and convert ATPG tests into scan

Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test sequences for use in manufacturing test

Slide 25 of 43 Sharif University of Technology Testability: Lecture 23

sequences for use in manufacturing test. sequences for use in manufacturing test.

SLIDE 26

Scan Design Rules

1. 1.

Use only clocked D Use only clocked D-

type of flip

type of flip-

flops for all state variables.

flops for all state variables. At l t PI i (t t t l) t b il bl f At l t PI i (t t t l) t b il bl f

2. 2.

At least one PI pin (test control) must be available for At least one PI pin (test control) must be available for test; more pins, if available, can be used. test; more pins, if available, can be used. All l k t b t ll d f PI All l k t b t ll d f PI

3. 3.

All clocks must be controlled from PIs. All clocks must be controlled from PIs.

4. 4.

Clocks must not feed data inputs of flip Clocks must not feed data inputs of flip-

flops.

flops.

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SLIDE 27

Correcting a Rule Violation Correcting a Rule Violation

All clocks must be controlled from PIs.

Comb. logic Comb. logic D1 D2 Q FF logic CK Q Comb. logic Comb. logic D1 D2 CK Q FF

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C

SLIDE 28

The Scan Concept

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Scan Flip-Flop (SFF)

D Master latch Slave latch TC Q

Logic

verhead

SD Q MUX CK D flip-flop CK Master open Slave open t TC (Test Control) Normal mode, D selected Scan mode, SD selected t

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Level-Sensitive Scan-Design Flip-Flop (LSSD-SFF)

Master latch Slave latch D Q Master latch Slave latch MCK Q SD D flip-flop SCK l MCK TCK Normal mode

Logic

verhead

TCK MCK TCK Scan mode

Slide 30 of 43 Sharif University of Technology Testability: Lecture 23

t SCK

SLIDE 31

Adding Scan Structure

PI PO SFF SFF Combinational logic SCANOUT SFF SFF logic SCANIN TC or TCK

Not show n: CK or MCK/SCK feed all

Slide 31 of 43 Sharif University of Technology Testability: Lecture 23

SCANIN

MCK/SCK feed all SFFs.

SLIDE 32

Tests for Full-Scan Circuits

Test generation for combinational logic only
Separate the test vectors and response data, based on

PI, PO and state (F) variables: ti = tiI, tiF i = 1, 2, n ri = riO, riF

Test application:
1. Scan-in tiF by setting the circuit in test mode

i

y g

2. Apply tiI

3. Observe riO 4. Set the circuit in functional mode and capture the response riF into scan register 5 Scan-out riF while scanning-in ti+ 1F by setting the circuit in test 5. Scan out ri while scanning in ti+ 1 by setting the circuit in test mode 6. i i + 1. Go to 2

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SLIDE 33

Combinational Test Vectors

I2 I1 O1 O2 PI PO Combinational logic SCANIN TC SCANOUT S2 S1 N2 N1 Present state Next state

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SLIDE 34

Combinational Test Vectors (cont’d)

Don’t care

r random

I2 I1 PI bits SCANIN S1 S2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 TC O1 O2 PO SCANOUT N1 N2

Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors

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nsff = number of scan flip-flops

SLIDE 35

Testing Steps

Scan register must be tested prior to application of scan

Scan register must be tested prior to application of scan test sequences test sequences test sequences. test sequences.

A shift sequence

A shift sequence 00110011 00110011 . . . of length . . . of length nsff

sff+ 4

4 in scan mode in scan mode (TC (TC 0) d ) d 00 00 01 01 11 11 d 10 10 i i i ll fli i i i ll fli fl d fl d (TC= (TC= 0) produces ) produces 00 00, , 01 01, , 11 11 and and 10 10 transitions in all flip transitions in all flip-

flops and

flops and

bserves the result at SCANOUT output.
bserves the result at SCANOUT output.

Covers most, if not all, single stuck

Covers most, if not all, single stuck-

at faults in FFs, and

at faults in FFs, and

verifies the correctness of the shift operation of the scan register.

Add

Add n + 4 to sequence length obtained in previous slide; to sequence length obtained in previous slide;

Add

Add nsff

sff+ 4

4 to sequence length obtained in previous slide; to sequence length obtained in previous slide;

Total scan test length:

Total scan test length: ( (ncomb

comb +

+ 2 2) ) nsff

sff +

+ ncomb

comb +

+ 4 4 clock periods clock periods.

Example:

Example: 2 2, ,000 000 scan flip scan flip-

flops,

flops, 500 500 comb. vectors, total

comb. vectors, total

scan test length ~ scan test length ~ 10 106 clocks. clocks.

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Multiple scan registers reduce test length.

SLIDE 36

Multiple Scan Registers

Multiple scan registers reduce test length.

Scan flip

Scan flip-flops can be distributed among any number of shift flops can be distributed among any number of shift

Scan flip

Scan flip flops can be distributed among any number of shift flops can be distributed among any number of shift registers, each having a separate registers, each having a separate scanin scanin and and scanout scanout pin. pin.

Sequence length is determined by the longest scan shift

Sequence length is determined by the longest scan shift register. register.

One

One test control test control (TC) pin is essential (scanin and scanout for (TC) pin is essential (scanin and scanout for

One

One test control test control (TC) pin is essential (scanin and scanout for (TC) pin is essential (scanin and scanout for each chain can share PI and PO pins, respectively). each chain can share PI and PO pins, respectively).

SFF Combinational logic PI/SCANIN PO/ SCANO UT

M U X

SFF SFF TC

Slide 36 of 43 Sharif University of Technology Testability: Lecture 23

CK

SLIDE 37

Scan Design Advantages/Disadvantages

Advantages:

Advantages:

1. 1.

By adding controllability/ By adding controllability/observability

bservability to the state variables, scan

to the state variables, scan design also eases functional testing. design also eases functional testing.

2. 2.

The testing problem is transformed from one of sequential circuit The testing problem is transformed from one of sequential circuit testing to one of combinational circuit testing. testing to one of combinational circuit testing.

Disadvantages:

Disadvantages:

1. 1.

IO pins: One pin necessary. IO pins: One pin necessary.

2. 2.

Additional area for latches/FFs ( Additional area for latches/FFs (area overhead area overhead) )

Gate overhead

Gate overhead = [ = [4 4 nsff

sff/(

/(ng+ 10 10nff

ff)] x

)] x 100 100% %, where , where ng = = comb. comb. gates gates; ; nff

ff =

= flip flip-

flops

flops;

ff ff

Example: Example: n ng = = 100 100k gates k gates, , nff

ff =

= 2 2k k flip flip-

flops

flops, overhead = , overhead = 6 6. .7 7%. %.

More accurate estimate must consider scan wiring and layout area.

More accurate estimate must consider scan wiring and layout area.

Slide 37 of 43 Sharif University of Technology Testability: Lecture 23

e accu ate est

ate ust co s de sca g a d ayout a ea

e accu ate est

ate ust co s de sca g a d ayout a ea

SLIDE 38

Scan Design Advantages/Disadvantages

3. 3.

Additional time required to latch the next state into the Additional time required to latch the next state into the i ( i ( d h d d h d) resisters ( resisters (speed overhead speed overhead)

Multiplexer delay added in combinational path; approx. two

Multiplexer delay added in combinational path; approx. two gate gate-

delays.

delays.

Flip

Flip-

flop output loading due to one additional fan

flop output loading due to one additional fan-

out;
ut;

approx.

approx. 5

5-

6

6%. %.

4

Additional time required to scan in/out test vectors and Additional time required to scan in/out test vectors and

4. 4.

Additional time required to scan in/out test vectors and Additional time required to scan in/out test vectors and responses ( responses (testing overhead) testing overhead) Cl k ti d di t ib ti i diffi lt Cl k ti d di t ib ti i diffi lt

5. 5.

Clock generation and distribution is more difficult. Clock generation and distribution is more difficult.

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SLIDE 39

ATPG Example: S5378

Original 2 781 Full-scan 2 781 Number of combinational gates 2,781 179 0 0% 2,781 179 15 66% Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead 0.0% 4,603 35/49 70 0% 15.66% 4,603 214/228 99 1% Gate overhead Number of faults PI/PO for ATPG Fault coverage 70.0% 70.9% 5,533 s 414 99.1% 100.0% 5 s 585 Fault coverage Fault efficiency CPU time on SUN Ultra II, 200MHz processor Number of ATPG vectors 414 414 585 105,662 Scan sequence length

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SLIDE 40

Automated Scan Design

Behavior, RTL, and logic Behavior, RTL, and logic Design and verification Scan design rule audits Rule violations Gate-level netlist rule audits Combinational Scan hard are Combinational ATPG Scan hardware insertion Scan netlist Combinational vectors Chip layout: Scan- chain optimization, timing verification Scan sequence and test program generation netlist vectors Scan chain order timing verification generation Design and test data for manufacturing Mask data Test program

Slide 40 of 43 Sharif University of Technology Testability: Lecture 23

manufacturing Mask data Test program

SLIDE 41

Timing and Power

Small delays in scan path and clock skew can cause race

Small delays in scan path and clock skew can cause race condition. condition.

Large delays in scan path require slower scan clock.

Dynamic multiplexers: Skew between TC and TC signals

Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs. can cause momentary shorting of D and SD inputs.

Random signal activity in combinational circuit during

Random signal activity in combinational circuit during scan can cause excessive power dissipation. scan can cause excessive power dissipation.

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SLIDE 42

Summary

Scan is the most popular DFT technique:

Rule

Rule-

based design

based design

Automated DFT hardware insertion

Combinational ATPG

Advantages:

Design automation

Design automation h f l h l f l d h f l h l f l d

High fault coverage; helpful in diagnosis

Hierarchical: scan

Hierarchical: scan-

testable modules are easily combined into

testable modules are easily combined into large scan large scan-

testable systems

testable systems

Moderate area (~

Moderate area (~ 10 10%) and speed (~ %) and speed (~ 5 5%) overheads %) overheads

Slide 42 of 43 Sharif University of Technology Testability: Lecture 23

SLIDE 43

Summary

Disadvantages:

Area overhead

Due to larger flip-flops Due to extra routing

Possible performance degradation

Extra gate delay due to the multiplexer

E i i l di d l d i i h fli fl

Extra capacitive loading delay due to scan wiring at the flip-flop output

Large test data volume and long test time

Basically a slow speed (DC) test

Not applicable to all designs (e.g. asynchronous designs, designs

violating scan design rules)

High power dissipation during testing

Slide 43 of 43 Sharif University of Technology Testability: Lecture 23

High power dissipation during testing