Design for Testability Outline Ad Hoc Design for Testability - PowerPoint PPT Presentation

Design for Testability Outline • Ad Hoc Design for Testability Techniques – Method of test points – Multiplexing and demultiplexing of test points – Time sharing of I/O for normal working and testing modes – Partitioning of registers and large combinational circuits • Scan-Path Design – Scan-path design concept – Controllability and observability by means of scan-path – Full and partial serial scan-paths – Non-serial scan design – Classical scan designs Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Method of Test Points: Block 1 is not observable, Block 1 Block 2 Block 2 is not controllable Improving controllability and observability: OP 1- controllability: CP = 0 - normal working mode Block 1 1 Block 2 CP = 1 - controlling Block 2 with signal 1 CP OP 0- controllability: CP = 1 - normal working mode Block 1 & Block 2 CP = 0 - controlling Block 2 with signal 0 CP Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Method of Test Points: Block 1 is not observable, Block 1 Block 2 Block 2 is not controllable Improving controllability: Normal working mode: CP1 = 0, CP2 = 1 Block 1 1 Controlling Block 2 with 1: Block 2 & CP1 = 1, CP2 = 1 Test Controlling Block 2 with 0: CP1 point CP2 = 0 CP2 Normal working mode: CP2 = 0 Block 1 MUX Block 2 Controlling Block 2 with 1: CP1 = 1, CP2 = 1 Test CP1 Controlling Block 2 with 0: point CP1 = 0, CP2 = 1 CP2 Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Multiplexing monitor points: To reduce the number of 0 output pins for observing 1 monitor points, OUT MUX multiplexer can be used: 2 n observation points are 2 n -1 replaced by a single output and n inputs to x 1 address a selected x 2 observation point x n Disadvantage: Only one observation Number of additional pins: (n + 1) point can be observed at MUX Number of observable points: [2 n ] a time Advantage: (n + 1) << 2 n Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Multiplexing monitor points: To reduce the number of output pins for observing 0 1 monitor points, multiplexer can be used: OUT MUX To reduce the number of inputs, a counter (or a 2 n -1 shift register) can be used to drive the address lines of the multiplexer c Counter Disadvantage : Only one observation point can be observed at Number of additional pins: 2 a time Nmber of observable points: [2 n ] Reset for counter ? Advantage: 2 < n << 2 n Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Multiplexing monitor points: Block 1 Block 2 0 1 OUT MUX 2 n -1 c Counter Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Demultiplexer for implementing control points: Normal Block 1 Block 2 MUX input lines Test mode Test point 0 CP1 CP2 1 x DMUX CPN 2 n -1 c Counter Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Demultiplexer for implementing control points: 0 CP1 CP2 1 To reduce the number of x DMUX N control input pins for controlling N pins points testpoints, demultiplexer and to add CPN 2 n -1 latch register are used x 1 x 2 x n Number of additional pins: (n + 1) Advantage: (n + 1) << N Number of control points: 2 n-1  N  2 n Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Demultiplexer for implementing control points: 0 CP1 CP2 1 To reduce the number of x DMUX inputs for addressing, a counter (or a shift register) can CPN be used to drive the address 2 n -1 lines of the demultiplexer c Counter Disadvantage: N clock times are required Number of additional pins: 2 between test vectors to set up Number of control points: N the proper control values Advantage: 2 << N Technical University Tallinn, ESTONIA

Time-sharing of outputs for monitoring To reduce the number of output pins for observing monitor points, time- sharing of working outputs can be introduced: no additional MUX outputs are needed To reduce the number of inputs, again counter or Original shift register can be used circuit if needed Advantage: 1 << N Number of additional pins: 1 Test time decreases Number of control points: N Technical University Tallinn, ESTONIA

Time-sharing of inputs for controlling To reduce the number of 0 CP1 input pins for controlling CP2 1 test points, time-sharing of working inputs can be introduced. Normal CPN N To reduce the number of input inputs for driving the lines address lines of DMUX demultiplexer, counter or shift register can be used if needed Advantage: 1 < N Number of additional pins: 1 Test time decreases Number of control points: N Technical University Tallinn, ESTONIA

Time-sharing of inputs for controlling Control lines 0 CP1 M1 CP2 1 M2 Normal CPn N Mn input lines DMUX Normal lines Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s Given a circuit : - CP1 and CP2 are not controllable - CP3 and CP4 are not observable DFT task: Improve the testability by using a single control input, no additional inputs/outputs allowed CP1 1 1 CP2 2 2 CP3 3 3 CP4 4 4 Block 1 Block 2 Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s Given a circuit : T Mode MUX CP3 and CP4 are not observable Coding: 0 Norm. 0  Improving the observability 1 1 Test Test mode T CP1 1 1 CP2 2 2 CP3 0 3 3 CP4 MUX 1 4 4 Block 1 Block 2 0 MUX 1 Result: A single pin T (test mode) is needed Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s Given a circuit : CP1 and CP2 are not controllable  Improving the controllability Coding: Q Mode DMUX MUX Counter T 00 Norm. 1 1 Q x 01 Contr 0 Decoder Test 1 0 10 0 DMUX 0 FF 1 CP1 MUX 1 1 0 1 DMUX 0 FF CP2 1 MUX 2 1 2 CP3 3 3 CP4 Result: 4 4 A single pin T is needed Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s z 1 MUX MUX 1 1 MUX MUX 2 2 Q Mode DMUX x 1 z 2 F 1 F 3 x 2 z 3 000 00 1 1 1 1 0 0 Norm y 1 x 3 x x x x 0 001 Contr 0 0 z 4 F 4 F 2 1 1 0 0 0 0 010 010 Test Counter T Counter 1 1 0 0 1 1 011 0 Obs 1 1 0 0 2 2 Obs 100 100 Decoder Decoder Q Obs 1 1 0 0 3 101 10 0 0 DMUX DMUX 0 0 FF 1 1 FF CP1 CP1 MUX 1 1 1 MUX1 1 1 0 0 Result: 1 1 1 1 A single MUX 2 CP 2 CP 2 2 MUX 2 2 2 2 2 2 pin T CP 3 3 3 3 3 4 3 is needed 4 CP4 Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Examples of good candidates for control points: – control, address, and data bus lines on bus-structured designs – enable/hold inputs of microprocessors – enable and read/write inputs to memory devices – clock and preset/clear inputs to memory devices (flip-flops, counters, ...) – data select inputs to multiplexers and demultiplexers – control lines on tristate devices Examples of good candidates for observation points: – stem lines associated with signals having high fanout – global feedback paths – redundant signal lines – outputs of logic devices having many inputs (multiplexers, parity generators) – outputs from state devices (flip-flops, counters, shift registers) – address, control and data busses Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Hazard control circuitry: Logical redundancy: Blue test 1 pattern is 0 Redundancy should be avoided: & 0 needed • If a redundant fault occurs, it may invalidate 1  0 some test for nonredundant faults 1 T & 1 1 • Redundant faults cause difficulty in calculating fault coverage • Much test generation time can be spent in & 1 trying to generate a test for a redundant fault  0 Redundancy intentionally added: Redundant AND-gate • Fault  0 not testable To eliminate hazards in combinational circuits Additional control input added: • To achieve high reliability (using error T = 1 - normal working mode detecting circuits) T = 0 - testing mode Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Fault redundancy: Testable error control circuitry: Error control circuitry: Decoder Decoder  1 Fault  E  1  Fault is detected No Error ? T Additional control input added: E = 1 if decoder is fault-free T  0 - normal working mode Fault  1 not testable T = 1 - testing mode Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques Partitioning of registers (counters): 16 bit counter divided into two 8-bit counters: Instead of 2 16 = 65536 IN OUT IN OUT clocks, 2x2 8 = 512 C REG 1 REG 2 CL clocks needed CL If tested in parallel, only 256 clocks needed CP: Tester Data CP: Tester Data CP: Data Inhibit CP: Data Inhibit & IN OUT & & IN OUT REG 2 & REG 1 CL CL C & & OP CP: Clock Inhibit CP: Tester Clock Technical University Tallinn, ESTONIA