21. Design for Testability 40 J. A. Abraham 60 Department of - - PowerPoint PPT Presentation

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• 21. Design for Testability
• J. A. Abraham

Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2015

November 11, 2015

ECE Department, University of Texas at Austin Lecture 21. Design for Testability

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Design for Testability (DFT)

Reduce costs associated with testing complex circuit Design circuit so that it will be easier to test Increase accessibility of internal nodes

Controllability: ability to establish specific signal value at each internal node by setting inputs Observability: ability to determine internal values by controlling inputs and observing outputs

Ensure predictable circuit responses Tradeoffs

Technical: area, I/O pins, performance Economic: design time, yield, time to revenue

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Testable Sequential Circuits

Sequential circuits are very difficult to test Design the internal memory elements to be part of a shifter register chain to provide controllability,

• bservability through serial

shifts With scan chain, problem of testing any circuit reduces to testing the combinational logic

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Level-Sensitive Scan Design (LSSD)

Structured DFT developed at IBM

All internal storage implemented in hazard-free polarity-hold latches (SRLs), part of a scan chain

Latches controlled by two or more non-overlapping clocks, with rules for clocking

All clock inputs to SRLs must be in their off states when primary inputs (PIs) are “off” Clock signal at any clock input to an SRL must be controlled from one or more clock PIs No clock can be ANDed with another clock Clock PIs cannot feed data inputs to latches, either directly or through combinational logic

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Scan Chains

Convert each flip-flop to a scan register

Only costs one extra multiplexer

Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register Contents of flops can be scanned out and new values scanned in

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Scannable Flip-Flops

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Boundary Scan

Testing boards is also difficult

Need to verify solder joints are good Drive a pin to 0, then to 1 Check that all connected pins get the values

Single-sided PC boards with “through-hole” construction used “bed of nails” to contact pins of chip on the back side of the board SMT and BGA boards cannot easily contact pins Build capability of observing and controlling pins into each chip to make board test easier

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Boundary Scan (IEEE 1149.1)

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Boundary Scan Example

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Boundary Scan Interface

Boundary scan is accessed through five pins

TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional)

Chips with internal scan chains can access the chains through boundary scan for unified test strategy

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IDDQ Testing

Measure quiescent power supply current of CMOS circuits for selected test vectors Example, microprocessor has nanoamps of current with no faults; many defects (shorts, for example) cause much higher currents Direct relationship found (Sandia Labs., HP, Phillips) between IDDQ test acceptance rates and quality, reliability of ICs Only need to activate site of potential defect (no need to propagate errors) Leakage current in very large chips may overwhelm the abnormal current due to a fault in one gate

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IDDQ Testing, Cont’d

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Built-In Self Test (BIST)

Increasing circuit complexity, tester cost Interest in techniques which integrate some tester capabilities

• n the chip

Reduce tester costs Test circuits at speed (more thoroughly)

Approach:

Compress test responses into “signature” Pseudo-random (or pseudo-exhaustive) pattern generator (PRG) on the chip

Integrating pattern generation and response evaluation

• n chip – BIST

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Pseudo-Random Sequence Generator (PRSG)

Linear Feedback Shift Register

Shift register with input taken from XOR of state Pseudo-Random Sequence Generator (or Pseudo-Random Pattern Generator (PRPG), or Linear Feedback Shift Register (LFSR))

Step Q 111 1 110 2 101 3 010 4 100 5 001 6 011 7 111 (repeats)

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Example of BIST

Technique called STUMPS (from IBM)

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Testability Issues – Custom Microprocessors

Chip complexity, large volumes, costs Area/performance penalties Fault (defect) coverage goals Test generation (fault simulation) costs Development time Tester time (manufacturing costs) ASICs generally use a “full scan” methodology for testability Some of the ad-hoc techniques used in custom microprocessors will be described in the following slides

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Testability Features of the Motorola 68020

Chip Statistics:

Process: 2µ HCMOS Die Size: 375 × 347 mils Transistor count: 200K

Test Overhead

Test Logic Area: < 3% Test Microcode: < 2% Test routing shared with functional routing to keep chip area down Bus structure helped create test partitioning for embedded structures Tradeoff of extra time to produce ad-hoc test logic with expected higher yield

Test techniques for ROMs, PLAs, Cache Test mode not available to customers (Why??)

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Testing Scheme for ROMs in the 68000 Family

Initial schemes for testing 68000 family control structures involved bussing nanoROM outputs off-chip via the address bus in test mode Could not test at speed since nanoROM output buffers were not sized to drive a bus Only nanobits were observable, and the PLAs, microROM and nanoROM had to be tested as one large sequential machine Test sequences were lengthy and difficult to write Tests were also microcode dependent

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Testability Techniques for 68020 ROMs

Used test mode to force next microcode address (NMA) from data pins Data pins also control a MUX for both micro and nano ROM

• utputs, which are moved to the BC bus, into the data

section of the execution unit, and to the address bus which can be observed Exhaustive testing of the 2K ROM entries 32 bits of ROM visible every 2 clocks Four passes of tests needed to read the 110

• utputs of the two ROMs

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Microrom Test in MC68881 Floating Point Co-processor

ROM physically split into two sections In test mode, ROM is addressed directly through the command register Exhaustive addresses fed to ROM in a “ping-pong” fashion (address/address complement) Outputs of ROM go to two 16-bit signature registers (using CCITT-16 polynomial x15 + x12 + x5 + 1) Monitor both the quotient and final signature serially on a test pin (Probability of aliasing 2−(n+m−1))

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MC68881 NanoROM Test

NanoROM physically located between the microROM and the execution unit (ECU), and outputs fed to ECU

No functional path for nanoROM to access signature registers

In test mode, nanoROM columns coupled with the microROM columns (with additional columns of nanoROM multiplexed to signature register)

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MC68881 Entry PLA Test

Four entry PLAs, A0, A1, A2 and A3

A0 PLA contains the entry point reset vectors and is completely tested functionally A1–A3 tested like the ROMs

Command register generates patterns and outputs are routed through a bus to the signature register Test patterns generated using PLA test generator PLA Inputs Outputs Products A1 6 10 23 A2 13 10 133 A3 5 10 28 Response 25 25 56

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Built-in Self Test in the Intel 80386

Normal PLA inputs disabled during test and output of pseudorandom generator provides exhaustive set of tests to AND-plane input CROM tested with binary counter (exhaustive test) Responses compressed using multiple-input signature registers Test transistors: 2.7% Area overhead for BIST: 1.8% Transistor sites tested with BIST: 52.5% Area tested: 18.6%

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Testing Cache Memory Arrays in MC68030

Cache cell layout design is resistant to both bridging defects and capacitive coupling

Most likely bridging defect is between adjacent metal bit lines

Memory fault model:

One or more cells stuck at 0 or 1 Coupling between cells

11n March Test (Marinescu, 1982) Refresh and data retention tests for the dynamic memory cells

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Test Architecture of MC68040

Utilizes three different DFT methods

Functional tests for data paths with normal mode instructions Ad-hoc test modes constructed for testing on-chip memory arrays and on-chip phase-locked loop Extension of existing functional snoop logic to allow arrays to be accessed from the bus similar to a static RAM array Structured custom scan approach for ROM, PLA and control areas

Global test bus driven from two 5-bit registers coordinates test logic IEEE 1149.1 boundary scan test interface

Boundary scan data register shared with scan logic

Test overhead:

18,560 devices, 1.55% of total number of devices 3.15% of total die area, including global test signal routing

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MC68040 DFT Method Coverage

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MC68040 Scan Chain and Timing

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BIST in IBM Risc System/6000

LSSD with pseudo-random BIST

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Common Engineering Processor (COP), bus, on-card sequencer (OCS), engineering support processor

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Common on-chip Processor (COP) in IBM RS/6000

Hardware for pseudo-random vector generation and result compression (31-bit LFSR)

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Small processor controls

• peration

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BIST in IBM/Motorola Power-PC

Variety of test techniques applied to the Power-PC 603

Full LSSD test of logic BIST of “large” embedded RAMS Functional test of small RAMS IDDQ tests

BIST for cache and tag RAMs

Functional vectors (good for data cache, not instruction cache) and random BIST (size, complexity, test coverage) not applicable

Use modified march test of Dekker (1988) log2 n pattern for data Overhead: BIST is 2.9% of RAM array, 0.58% of total chip Performance impact: less than 100 pS due to extra MUX input leg All four RAMs tested in parallel, 2.5 mS at 80 MHz

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Testing Embedded Cores in a System on Chip

Source/Sink for test: Embedded processor Test access mechanisms: Busses Core test “wrapper” for Test Access Interface (TAI) Lagged Fibonnaci Sequence random pattern generator Xn = (Xn24 + Xn55) mod m, n ≥ 55 Primitive polynomial: X55 + X24 + 1 Period: 2321 × (255 − 1) No multiplication necessary x86 code for generator: LDR R5,[R0],#4 LDR R6,[R1],#4 ADD R5,R5,R6 STR R5,[R2],#4 AND R0,R0,R3 AND R1,R1,R3 AND R2,R2,R3

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Issues with Built-In Self Test

Technique can run test sequences at operating frequencies and capture results within the chip Pseudorandom pattern generators, signature analyzers Can also use weighted random patterns or deterministic patterns Example (Synopsys): (Deterministic Logic BIST Problems: Hardware overhead Test power Non-functional modes during test

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Industry Issues with Processor Testing

Concern with detecting real defects Small delay defects due to process variations, power droops and capacitive coupling Cause a shift in the speed of the part Problems with logic BIST (same issues with scan AC tests) Overheads on chip False paths tested Test operating conditions different from normal operating modes

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Software-Based (Native-Mode) Self Test for Processors

Why not use functional capabilities of processors to replace BIST hardware?

No additional hardware

Reduce test costs by using low-cost testers Increase coverage of delay defects and increase yield by testing native No issues with excessive power consumption during test Developed at University of Texas (Int’l Test Conference 1998) Application to processors at Intel (Int’l Test Conference 2002)

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Software Based Self Test

Advantages Minimized DFT circuitry Reduced external tester per- formance Excessive test power and

• ver-testing

eliminated

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Native-Mode Signature Compression

Pseudo-code for software signature analyzer // S: general register or memory, holds signature for each register Ri to be compressed { Shift Right Through Carry(Ri); if (Carry) {S = XOR(S, feedback polynomial)}; S = XOR(S, Ri); }

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Intel Functional BIST

Functional Random Instruction Testing at Speed (FRITS) applied to Itanium processor family and Pentium 4 line (ITC 2002) Tests (kernels) are instruction sequences Kernels loaded into cache and executed in real time during test application They generate and execute pseudo-random or directed sequences of machine code On Pentium-4, FRITS added 5% unique coverage to manual tests screened 10% – 15% of chips which passed wafer sort/package tests, but failed system tests enabled low-cost testers: 40% increase in defect screening on structural tester Kernels execute 20 loops in ≈ 8 mSecs

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Are Random Tests Sufficient?

Intel implementation involved code in the cache which generated random instruction sequences Interest in generating instructions targeting faults Possible to generate instruction sequences which will test for an internal stuck-at fault in a module In order to deal with defects in DSM technologies, need to target small delay defects Automatically generate instruction sequences which will target small delay defects in an internal module

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RT Level Test Generation for Hard-to Detect Faults

Overview

Map gate level stuck-at fault to RTL Capture the propagation constraints as an LTL property Generate a witness for the LTL property using Bounded Model Checking All required constraints available in RTL Use SMT based Bounded Model Checking Scaling with cone-of-influence reduction

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Modeling Stuck-at Faults in RTL

Approach Assume one to one match between flops in RTL and gate netlist Identify flops/primary outputs o1, o2, ..., on in output cone of the fault Identify the boolean function for each of the output flops/primary outputs. Ex ok = fk(i1, i2, ..., im) Identify the Boolean function for the output flops with the fault inserted. Ex of

k = ff k (i1, i2, ..., im)

Fault condition : faultk = fk(i1, i2, ..., im) ⊕ ff

k (i1, i2, ..., im)

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Modeling Stuck-at Faults in RTL

Example always @(posedge clk) sum <= PI ⊕ sum; sum = (PI ∧ ¬sum) ∨ (¬PI ∧ sum) sumf = PI ∧ ¬sum faultsum = sum ⊕ sumf = ¬PI ∧ sum

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Modeling Stuck-at Faults in RTL

Example always @(posedge clk) sum′f <= PIf ⊕ sumf; assign faultsum = (¬PIf ∧ sumf); assign sumf = (faultsum?¬sum′f : sum′f);

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Capturing Fault Observability

Naive Approach Let M be the DUT and Mf be the faulty machine SMT good = I ∧ M0 ∧ ... ∧ Mn−1 SMT faulty = I ∧ Mf

0 ∧ ... ∧ Mf n−1

Product Machine, SMT M×Mf = SMT good ∧ SMT faulty Observability Condition: F(

• ∀i

(Outputi ⊕ Outputf

i ))

Issues Two unrolled copies of the machine Search space is large

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Capturing Fault Observability

Approach Identify error(D/ ¯ D) propagation paths in RTL for given fault(Dependency Graph) Capture propagation path conditions as observability properties Oj

p

Property for fault excitation and propagation F(Cp ∧ Oj

p)

Scalability by constraining the search space Bounded Cone of Influence Reduction

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RTL Test Generation for Hard-to-Detect Faults

Experimental Setup OR1200 RISC processor was DUT EBMC Model checker / Boolector SMT solver Bound of pipleine depth + 1 Focused on hard to detect faults in control logic Commercial ATPG to seive out easy to detect stuck-at faults 78% Fault coverage by commercial ATPG

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RT Level Test Generation for Hard-to Detect Faults

Experimental Results using SMT Solver

Module ATPG FC(%) Flts. SAT based method Naive Observability Method FC(%) # TO T(sec) FC(%) # TO T(sec) if 80.35 328 84.11 310 96.18 88.49 161 95.13 ctrl 63.21 832 65.97 817 83.12 97.15 59 69.72

• prmuxes

73.66 378 76.09 354 95.49 98.26 6 57.46 sprs 89.59 393 90.85 381 93.71 93.78 57 90.27 freeze 82.94 17 99.14 2 64.41 100 43.51 rf 78.59 7444 80.50 7268 97.57 90.21 463 69.83 except 72.69 1263 73.48 1209 98.63 92.79 128 96.19 Overall 78.05 10655 79.17 10343 96.23 93.86 874 76.11 FC(%) : Fault Coverage in % # TO : # of Timed Out faults T(sec) : Average Time for generating a test for a fault in seconds

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Experimental Results, Structural Observability

Module FC(%) # TO T(sec) if 98.17 25 23.14 ctrl 99.21 8 21.16

• prmuxes

100 19.33 sprs 97.53 12 18.39 freeze 100 10.48 rf 98.37 172 22.85 except 97.63 69 38.14 Overall 98.87 454 24.23 FC(%) : Fault Coverage in % # Faults : # of Undetected Collapsed Faults # TO : # of Timed Out faults T(sec) : Average Time for generating a test for a fault in seconds

Summary of Results Functional fault coverage of ≈99% for OR1200 processor SMT based approach was 4x faster than SAT

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Detecting Delay Defects After Manufacturing

Necessary to detect “small-delay defects” Delay defects which don’t affect performance soon after manufacture could be reliability hazards Need Path Delay Tests to ensure that defective parts are screened out

Difficult to apply two-pattern tests in scan mode Requires precise control of clocks for high-speed circuits If capture clocks are based on the system clock, there is no information on the slack for the path

Solution: On-chip programmable capture mechanism

Ability to capture faster than at-speed

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Delay Lines for On-Chip Programmable Capture

Source: R. Tayade, et al.

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System for On-Chip Programmable Capture

Source: R. Tayade, et al.

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