Introducing Formal Validation in an Asynchronous Circuit Design Flow - - PowerPoint PPT Presentation

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Introducing Formal Validation in an Asynchronous Circuit Design Flow

• D. Borrione, M. Boubekeur, E. Dumitrescu (VDS)
• M. Renaudin, J.B. Rigaud, A. Sirianni (CIS)

TIMA Laboratory 46 avenue Felix Viallet 38031 Grenoble Cedex France

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Contents

H Asynchronous circuit design flow H Validation of specifications H On-going experiments

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Global Design Flow

CHP Specification Petri Net + DFG

Validation by Simulation Asynchronous Synthesis Behavioral VHDL Asynchronous VHDL netlist Standard design tools VHDL Simulator Back-end tools

TAST (Tool for Asynchronous circuits SynThesis)

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TAST Compiler : Compiling Specifications

CHP Code CHP Compiler Petri Net + DFG

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TAST Model Generator Validation by Simulation

Simulation Model Generator Behavioral Asynchronous VHDL Model

VHDL Custom Libraries for Simulation

Petri Net + DFG

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TAST Synthesizer Asynchronous Synthesis

Custom Cell Libraries

DTL Compliance Checker µP Flavor Synthesizer QDI Flavor Synthesizer VHDL Gate Level Netlist

Std Cell Libraries

Synthesizable PN + DFG

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Characteristic Features of CHP

component NAME Port (….) Declaration of local objects begin List of concurrent processes and interconnected component instances end NAME;

Communications: ! (send) ? (receive) # (probe) Control structures: deterministic/non-deterministic selection and loop Asynchronous circuit specific types: signed/unsigned multi-rail

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Data encoding

rail0 rail1 rail2 MR[3] type variable

MR[b] : multi-rail « one-hot » encoding

⇒ represents values in the range 0..b-1 Example : MR[3] codes values in the range 0..2 000: no data 001: "0" 010: "1" 100: "2"

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Data encoding : communication channels

DR type channel rail0 rail1 ack

MR (multi-rail) encoding + additional acknowledge signal, to support handshaking communication protocols

Example : dual rail channel

rail0 rail1 ack 1 2 3 4

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Selector

C(2) C(1) C(0) C_ack S1(1) S1(0) S1_ack S2(1) S2(0) S2_ack

C E S1 S2

E(1) E(0) E_ack

Data Flow Circuit Example

Specified behavior (DI, one-hot)

If ctrl = "001" then E is read and then written on S1. If ctrl = "010" then E is read and then written on S2. If ctrl = "100" then E is read and then written in parallel on S1 and S2.

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Selector

C(2) C(1) C(0) C_ack S1(1) S1(0) S1_ack S2(1) S2(0) S2_ack

C E S1 S2

E(1) E(0) E_ack COMPONENT Selector PORT (E: IN DR; C: IN MR[3][1]; S1, S2 : OUT DR ) BEGIN PROCESS main PORT (C: IN MR[3][1]; E: IN DR; S1, S2 : OUT DR ) variable x: DR; variable ctrl: MR[3][1]; [ *[C?ctrl; [ ctrl = "0"[3] => E?x; S1!x @ ctrl = "1"[3] => E?x; S2!x @ ctrl = "2"[3] => E?x; S1!x, S2!x ] ] ] END Selector ;

CHP Circuit Specification

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Petri Net of Selector

E ? x; S2 !x ;

P0

ctrl =″1″ [3] ctrl =″2″ [3]

T1 T0 T10 T14

T2

P9 P5

ctrl=″0″ [3] E ? x; S1 !x ;

T14 T13 T15

P7

P8 P6 P1

S2 !x ; S1 !x ; E ? x;

T4 T9 T5

P4 P3 P2

C ?ctrl ;

T3

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Asynchronous Synthesis

C3r E_0 E_ack E_1 S1_0 S1_ack S1_1 S2_0 S2_ack S2_1 C_ack C_2, C_1, C_0 C3r C3r C3r C3r C3r C2

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Model checking Environment Constraints Petri Net - DFG PN with Expanded Communications Pseudo-synchronous VHDL Behavioral Model QDI Flavor Synthesizer VHDL Gate Level Netlist

Formal Verification Flow

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Translating Petri Net to Verifiable VHDL

The Petri Net of the CHP specification gives the control flow actions are attached to places conditions are attached to transitions Places with communication are considered state holding Abstract communications have to be expanded, w.r.t. the data type of the interconnection signals the hand-shaking protocol Carefully select a target VHDL subset and style RTL, synthesizable, verifiable by commercial tools artificial clock added for making execution cycles visible

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P_2 P_1

((C="001" Or C="010")

• r C="100")

C= ″000″ Ctrl <= C ; C_ack <= ‘0’ ; C_ack <= ‘1’ ;

P C ? ctrl

C ? Ctrl

CHP declaration

C : IN MR [3][1]; Variable Ctrl : MR [3][1]; Signal C : IN bit_vector (2 downto 0); Signal C_ack : OUT bit; --Acknowledgement Signal Ctrl : Bit_vector (2 downto 0);

Translation of communications : Read

P

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S_ack =’0’ S_ack= ’1’

P_1 P_2

S <= ’00’ ; S <= X ;

P

P

S ! x

Translation of communications : Write

S ! X CHP declaration

S : OUT DR Variable X : DR; Signal S : out Bit_vector (1 downto 0); Signal S_ack : in bit; -- Acknowledgement Signal X : Bit_vector (1 downto 0);

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Selector

C(2) C(1) C(0) C_ack S1(1) S1(0) S1_ack S2(1) S2(0) S2_ack

C E S1 S2

E(1) E(0) E_ack

Environment

Constraints on the environment

Input channel constraint C_Env1 After Ex11_Ent : P0 = True Eventually (Ex11_Ent : C = x "1" or Ex11_Ent : C = x "2" or Ex11_Ent : C = x "4") and Ex11_Ent : P0 = True Meaning : Each time place P0 is active, an incoming control request will eventually occur.

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Resulting Verifiable VHDL Model

entity EX11_Ent is port ( C : in bit_vector(2 downto 0); C_a : out bit; S1, S2 : out bit_vector(1 downto 0); S1_a, S2_a : in bit; … clk, rst : in bit); end EX11_Ent; architecture EX11_a of EX11_Ent is signal Pi, P0, …: boolean; begin process(clk, rst) begin if (rst='0') then

• - initialization at reset

S1 <="00"; S2 <="00"; C_a <= '1'; E_a <= '1'; Pi <= true; … elsif clk'event and clk='1' then

• - fictitious clock edge

… if P7_1 then EX11_MAIN_X <= E; E_a <= '0'; end if; -- start of read action at place P7 if P7_2 then E_a <= '1'; end if;

• - acknowledge hand-shake at expansion of P7

... end if; end process; end EX11_a;

E ? x; P7

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C_Env2 After : Ex11_Ent:C_ack = 0 Eventually : Ex11_Ent:C = x "0"

Other Input Channel Constraints

Each time request C is acknowledged (C_ack = 0), C will eventually return to zero. A request is stable until it is acknowledged

Stable_C After : Ex11_Ent:C = x "1" or EX11_Ent:C = x "2" or EX11_Ent:C = x "4" Always : Exp1_Ent:C = stable Unless : Exp1_Ent:C_ack = 0

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Output Channel Constraints

S1_Env1 After : Exp1_Ent:S1(1) = 1 or Exp1_Ent:S1(0) = 1 Eventually : Exp1_Ent:S1_ack = 0 After a request on S (S1(1) = 1 or S1(0) = 1), an acknowledgement will eventually be received (S1_ack = 0). S1_Env2 After : Exp1_Ent:S1 = x"0" Eventually : Exp1_Ent:S1_ack = 1 After the write transaction on channel S is finished (S = x "0"), the acknowledgement will eventually be deactivated (S_ack = 1).

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Some verified properties

A1) After : EX11_Ent:P01 = True and EX11_Ent:C = x "1" Eventually : EX11_Ent:S1(1) = 1 or EX11_Ent:S1(0) = 1 A2) After : EX11_Ent:P01 = True and EX11_Ent:C = x "2" Eventually : EX11_Ent:S2(1) = 1 or EX11_Ent:S2(0) = 1 A3) After : EX11_Ent:P01 = True and EX11_Ent:C = x "4" Eventually : (EX11_Ent:S1(1) = 1 or EX11_Ent:S1(0) = 1) and (EX_Ent:S2(1) = 1 or EX11_Ent: S2(0) = 1)

Accessibility of Petri Net places/path

Meaning of property A1 : If place P01 is active and an incoming request C = x"1" arrives, then a write will eventually occur on S1.

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Refining the State Machine Model

H Current Petri Net: !One place marking combination = one FSM state

. Combinational explosion

!Objective: distinguish between

. Internal computation control . Synchronization from communication events

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Petri Net Transformations

S1 <= ex p1 S2 < = ex p2 1 T T S1 <= ex p1 S2 < = ex p2 T S <= C ? exp1 : exp2 not C T C S <= exp 1 1 S <= exp2

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Current work

H Develop validation strategies for classes of circuits H Verifying the asynchronous synthesis !Component libraries compliance to verifiable VHDL !Properties of the resulting asynchronous circuit

. No equivalence . Stuttering simulation