Clocking & Timing Asynchronous Self Timed Design Self Timed - - PowerPoint PPT Presentation
Advanced Digital IC-Design Overview Synchronous Clocking & Timing Asynchronous Self Timed Design Self Timed Design Synchronous Circuit Asynchronous Circuit Req Req Req Handshake Handshake A k Ack Ack A k Ack REG REG REG OUT
CLK
REG
Logic
D Q
REG
Logic
D Q
REG
D Q
IN OUT
Global synchronization Clock period > Max Delay (t logic + t R)
Req A k
Handshake Handshake
Req A k Req
REG
Logic
D Q
REG
Logic
D Q
IN OUT Ack Go Done Ack Ack Go Done
Local synchronization (handshaking): Request Acknowledge
Clocked Domain
Local
REG
Logic
D Q
REG
D Q
IN
Interface Interface
OUT Req Ack Req Ack
Clocked Domain
Local Clock
Asynchronous Environment
The purpose of the clock is to The purpose of the clock is to
Synchronize the registers on the chip with each other Synchronize the registers on the chip with the external world
Clock skew is a large problem
Registers Latches
Combinational
Latches Flip-flops
Logic State Comb. Logic State Comb. Logic State Comb. Logic State
Latch stores data when clock is low (high) Flip-Flop (or Register) stores data when clock rises (falls) Register: Edge Triggered Latch: Level Sensitive
Clk
D Clk Q
Latch
Clk
Register
D Clk Q
D Q D Q
Q on Clock Edge Q on Data
Clock skew
Spatial a iation in tempo all eq i alent Spatial variation in temporally equivalent clock edges
Clock jitter
Temporal variations in consecutive edges of the clock signal the clock signal
Both skew and jitter affects the cycle time Skew might lead to race through the registers Same clock at two
different locations on the chip
Clock feedthrough
VDD
0,5 1,5 2,5
Q
0,5 1
Time, ns
Clock feedthrough
Coupling in dynamic devices can lift the output
VDD (Always on)
Module 1 Global Clock Module 2
Data De- skew Enable 2 Enable 3 Phase Locked Loop
N
System Clock
CLK
f
SYS CLK
N f f M = ×
Local Clock Signals Module 3
N M On-Chip Clock Generation Clock Gating Clocked Modules
In tpd,reg tpd1 D R1 Q CLK Logic Block #1 tpd2 D R2 Q Logic Block #2 tpd3 D R3 Q D R4 Q Logic Block #3 Delay Delay Delay
The delay give clock skew
Example: 15 mm wire C = 300 fF R = 4 kΩ tpHL = 0.69RC = 0.8 ns
CLK
“Max frequency”
1 1 600 MHz 2 2 0.8 ns
pHL
t = = ×
Negative Skew Out
REG
Abs
REG
Log
REG REG
In
R
Positive Skew CLK
Data bus tjitter thold Clock line tjitter tsetup
jitter hold jitter setup
Ext. CLK
φ1
CLK
φ2 φ1
Large skew require large non-overlap
φ1 φ2
R t Branches Leaves
Clock Source
Root Trunk
All wires and buffers are carefully balanced
Clock
A balanced H- tree structure Achieves a skew control of ± 25 ps
H-tree X-tree
Power Hungry
Clock
Ph Deskew Control Delay Line Delay Line Phase Det.
Clock
AVG AVG AVG AVG AVG AVG AVG AVG AVG AVG
A A AVG AVG AVG
Clock Frequency 300MHz Transistors 10 Million Total Clock Load 3.75nF Clock Power 20W (out of 50W) Clock Levels 2 Driver Size 58cm Driver Size 58cm Clock Grid TSPC
Clock
R1
M U X
L L L R2 R3 L L L lk
adjacent registers.
adjacent registers.
clk Positive "clock skew"
clock signal has a period of 16ns. Register R setup time t S 0.5 ns Register R delay time t R 0.5 ns Logic L delay time t L 3.0 ns Mux delay time t M 1.0 ns
R1
M U X
L L L R2 R3 L L L lk
minimum clock period time if clock
Answer: The minimum clock period time is 10 ns clk Positive "clock skew" skew is disregarded R2 to R3, t R+ 3t L+ t S = 0.5+ 3* 3.0+ 0.5 = 10ns R2 to R2, t R+ 2t L+ t m+ t S = 0.5+ 2* 3.0+ 1.0+ 0.5 = 8ns R1 to R2, t R+ 2t L+ t m+ t S = 0.5+ 2* 3.0+ 1.0+ 0.5 = 8ns Answer: The minimum clock period time is 10 ns
Register R setup time t S 0.5 ns Register R delay time t R 0.5 ns Logic L delay time t L 3.0 ns Mux delay time t M 1.0 ns
R1
M U X
L L L R2 R3 L L L lk
minimum clock period time if there is 1ns positive clock skew
R2 to R3, t R+ 3t L+ t S-t SKEW = 0.5+ 3* 3.0+ 0.5-1 = 9ns Answer: The minimum clock period time is 9 ns clk Positive "clock skew" between adjacent registers.
Register R setup time t S 0.5 ns Register R delay time t R 0.5 ns Logic L delay time t L 3.0 ns Mux delay time t M 1.0 ns
R1
M U X
L L L R2 R3 L L L lk
minimum clock period time if there is 3ns positive clock skew
R2 to R2, t R+ 2t L+ t m+ t S = 0.5+ 2* 3.0+ 1.0+ 0.5 = 8ns (No skew in feedback) clk Positive "clock skew" between adjacent registers
Register R setup time t S 0.5 ns Register R delay time t R 0.5 ns Logic L delay time t L 3.0 ns Mux delay time t M 1.0 ns
R1
M U X
L L L R2 R3 L L L lk
maximum “clock skew” for the datapath, both positive and negative if
Negative skew - R2 to R3, 16-t R+ 3t L+ t S = 16-0.5-3* 3.0-0.5 = 6ns (6 ns for clk to R2 plus 10 ns for signal through logic) Positive skew - R1 to R2, t R+ t L+ t m+ t S = 0.5+ 3.0+ 1.0+ 0.5 = 5ns clk Positive "clock skew" the clock signal has a period of 16ns (R2 must close before signal arrives)
Register R setup time t S 0.5 ns Register R delay time t R 0.5 ns Logic L delay time t L 3.0 ns Mux delay time t M 1.0 ns
From asynchronous domains or From synchronous domains with different clock
Asynchronous Asynchronous system system synchronous synchronous t
periods
system system system system synchronization synchronization
Metastable state: possible output from a flip-flop
Aperture window t res is important t res Many designers are not aware of metastability important for MTBF Can occur if the setup t SU, hold time t H, or clock pulse width t PW of a flip-flop is not met
D Q DATA IN CLK Q1 DATA IN tW tSU tres tCO CLK Q1 “1” “0”
tW = Time window where input transition may cause a metastable condition tSU = Actual clock setup time for flip-flop tCO = Actual flip-flop propagation delay tres = Metastability resolution time
2 1 res CLK DATA
K t K f f
× × ×
Mean Time Between Failure (MTBF) is exponential t res is the slack time available for settling K and K are constants that are
K1 and K2 are constants that are characteristics of the flip-flop fCLK and fDATA are the frequency of the synchronizing clock and asynchronous data MTBF variations due to the metastability resolution time t res
11
2 1 res CLK DATA
K t K f f
MTBF e
× × ×
=
10
5
10
6
10
7
10
8
10
9
10
10
10
11
MTBF (seconds) 1000 years 1 year 1 month 1 day i tres (ns) 10
1
10
2
10
3
10
4
2 4 6 8 10 1 hour fDATA = 1 MHz FCLOCK = 10 MHz ACTEL ACT 1 Devices
t res = available slack time (ns)
D D FF1 FF2 Asynchronous input
Q1 Q2 D Q D Q
CLK Da Ds Synchronized signal
Q1 Q2
A5
Global low-skew clock
If D is in the aperture time (setup+ hold) of the flip flop – Q1 is uncertain However, FF2 might have registered a proper data before Much higher probability for a stable Q2 than Q1
CLK D Timing Violation
Q1
Asynchronous input
D
Q2
Leads to Metastability Correct in next register if Q1 have become stable D Q D Q
CLK Da Ds FF1 FF2 Synchronized signal
Q1 Q2
D CLK
Synchronous Clock skew Worst case delay sets the speed Asynchronous Non-trivial design task due to race S l i Solution Self-timed design?
Common arguments:
Low power - Maybe Low power Maybe High speed - Sometimes Low emission - Yes Low sensitivity to Process, Voltage, and Temperature variations - Yes N l k di t ib ti d ti i bl Y No clock distribution and timing problems – Yes No clock skew problems - Yes Less interference to analog domain - Yes
100% is not unusual 100% is not unusual
Synchron
Asynchron
Synchron DSP Asynchron DSP
Source: James Awad, Octasic Semiconductor
logic logic handshake handshake go done go done req req req data data data ack ack ack
1.The sender issues a request 2.The receiver replies by an acknowledge 3.Then the sender sends the data
Module 1 Module 2
If the sender initiates the data transfer The transfer channel is a push-channel If the receiver initiates the transfer The channel is a pull-channel
n
On both raising and falling edges
(No return-to-zero
(No return-to-zero transitions)
produces an acknowledge 1 Data 2 3 Req Ack Cycle 1 Cycle 2
1. The sender issues data and sets Req to high 2. The receiver absorbs the data and sets Ack to high 3 The sender responds by setting Req to low
Return-to- zero transitions
3. The sender responds by setting Req to low 4. The receiver acknowledges by setting Ack to low 1 Data 3 2 Req Ack Cycle 1 Cycle 2 3 4
A B Q
Q A R S
Static
1 Q 1 Q 1 1 1 A
B R A
VDD
B
Dynamic
Q B
Q B B A
Implementation using Muller-C elements
A B Q 1 Q 1 Q 1 1 1
Data ready
C
Sender Logic
R
Receiver Logic
Data accepted
Data n
0 1 1 Q 0 Q
Q
1 1 1
Req Ack
1 1 0 1
Q
Implementation using Muller-C elements
Data Data ready Data accepted Req S C C Sender logic Receiver logic Handshake logic Ack
Send your slides to me, latest the night before your presentation Preferred format - .ppt You will be evaluated by your fiends Please look at the template: Please look at the template:
http: / / www.eit.lth.se/ course/ eti135 -> Presentations
Solutions to 4 hand-in Solutions to 4 hand in assignments are required, see
http: / / www.eit.lth.se/ course/ eti135 -> Home Exercises
Deadline: March 8 Invited Lecture
Static tim ing analysis 11/ 02, 15.15-17.00 Design for test is canceled es g
design of synchronous circuits and which normally leads to the g y y most efficient circuits, due to the extensive use of timing assumptions (example: Amulet 2 processor).
introduced by Ivan Sutherland in his 1988 Turing Award lecture (example: Amulet 1 processor)
Muller’s pioneering work in the 1950s.
Rail scheme (LEDR).
From [Horowitz]
B0
Start
PDN PDN
Dual
A&A B&B
Start
B1
B Dual Rail Used in
Phase B0 B1 B Comment Precharge Not Done Evaluation 1 1 Done Evaluation 1 1 Done Illegal 1 1
Used in self-timed modules
In R1 F1 Hand Shake
Start Done
Ack Req
R2 F2 Hand Shake
Start Done
Ack Req
R3 F3 Hand Shake
Start Done
Ack Req
Out tp1 tp3 tp2
Hand Shake
Ack Req
Hand Shake
Ack Req
Shake
Start Done
Ack
Shake
Start Done
Ack
Delay Model
e.g. Critical Path
Delay Model
e.g. Critical Path
In R1 F1 R2 F2 Out
Delay replicas matched Delay replicas matched to critical paths Worst-case delay Sensitive to process variations Small circuit overhead
Hand
Req
Hand
Req
Hand
Req
In R1 Self- timed Hand Shake
Start Done
Ack
R2
Delay- Model
Hand Shake
Start Done
Ack
R3 Self- timed Hand Shake
Start Done
Ack
Out tp1 tp3 tp2
Done C C C
Linear Pipelines (only one input and output)
Non-Linear Pipelines
Fork Join Conditional Split Conditional Join
Global Synchronous Asynchronous racticed
GALS
Traditional
Globally Asynchronous Locally Synchronous
Local Pr
Globally Asynchronous Locally Synchronous to Avoid Skew
Input reference Input delay state
p
Digitally Controlled Oscillator Delay control counter
Cycle counter up/down Multiplication factor
factor Output clock
Phase Detector VCO
Voltage-contr.
Loop Filter
Off-Chip Clock On-Chip Clock
Divider