Principles Of Digital Design Discussion: RTL Storage Components Shift Register Timing Register File Timing RAM Up/Down Counter FIFO Queue
Shift Register Timing Problem: Complete the timing diagram for the shift register shown. Assume the register stores 0’s initially and inputs I L and I R are always 0. I 3 I 2 I 1 I 0 I R Clk I L I 3 I 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 I 1 Selector Selector Selector Selector I 0 S 1 S 1 S 0 S 0 D 3 Q 3 D 2 Q 2 D 1 Q 1 D 0 Q 0 Q 3 Q 2 Q 1 Clk Q 0 Y 3 Y 2 Y 1 Y 0 t 0 t 1 t 2 t 3 t 4 Shifter Timing Diagram Shifter Schematic Present State Operation S 1 S 0 0 0 No Shift Load Input 0 1 Shift Left 1 0 Shift Right 1 1 Shifter Truth Table 2 DIGITAL DESIGN 101, University of California RTL Storage Components
Shift Register Timing Solution: Complete the timing diagram… I 3 I 2 I 1 I 0 I R Clk I L I 3 I 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 I 1 Selector Selector Selector Selector I 0 S 1 S 1 S 0 S 0 D 3 Q 3 D 2 Q 2 D 1 Q 1 D 0 Q 0 Q 3 Q 2 Q 1 Clk Q 0 Y 3 Y 2 Y 1 Y 0 t 0 t 1 t 2 t 3 t 4 Shifter Timing Diagram Shifter Schematic Present State Operation S 1 S 0 0 0 No Shift Load Input 0 1 Shift Left 1 0 Shift Right 1 1 Shifter Truth Table 3 DIGITAL DESIGN 101, University of California RTL Storage Components
Register File Timing Problem: Complete the timing diagram for the register file (RF) shown. Assume RF stores 0’s initially, REB is always 0, and REA is always 1. RAA 1 RAA 0 RAB 1 RAB 0 WA 1 WA 0 REB REA WE I 3 I 2 I 1 I 0 0 2-to-4 2-to-4 Read Read RFC RFC RFC RFC Decoder Decoder Clk I 3 0 0 1 I 2 I 1 RFC RFC RFC RFC I 0 1 1 2 WE WA 3 RFC RFC RFC RFC RA 1 3 2 2 A 3 3 A 2 2-to-4 RFC RFC RFC RFC A 1 Write 3 Decoder A 0 3 t 0 t 1 t 2 t 3 t 4 B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 RF Schematic RF Timing Diagram 4 DIGITAL DESIGN 101, University of California RTL Storage Components
Register File Timing Solution: Complete the timing diagram… RAA 1 RAA 0 RAB 1 RAB 0 WA 1 WA 0 REB REA WE I 3 I 2 I 1 I 0 0 2-to-4 2-to-4 Read Read RFC RFC RFC RFC Decoder Decoder Clk I 3 0 0 1 I 2 I 1 RFC RFC RFC RFC I 0 1 1 2 WE WA 3 RFC RFC RFC RFC RA 1 3 2 2 A 3 3 A 2 2-to-4 RFC RFC RFC RFC A 1 Write 3 Decoder A 0 3 t 0 t 1 t 2 t 3 t 4 B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 RF Schematic RF Timing Diagram 5 DIGITAL DESIGN 101, University of California RTL Storage Components
RAM Timing Timing diagram Clk Reading address 1 I 3 Writing 1110 to address 3 I 2 Reading address 3 I 1 Writing 0110 to address 3 I 0 WE WA 3 RA 1 3 A 3 A 2 A 1 A 0 6 DIGITAL DESIGN 101, University of California RTL Storage Components
1M RAM Design Build 1M x 32 RAM using 256 K x 32 RAM chips. . . . . . . I 1 I 31 I 0 A 17 . . . . . . A 1 2 18 x 32 RAM A 0 CS RWS . . . . . . . . . . . . O 31 O 1 O 0 . . . Memory address and content 7 DIGITAL DESIGN 101, University of California RTL Storage Components
1M x 32 RAM design with 256K x 32 RAMs Input bus RWS 18 Addresses 2 2-to-4 decoder I 0 3 2 1 0 A . . CS M 0 . RWS O Four 256K RAM 2 18 -1 I 2 18 A 256 K = 2 8 X 2 10 = 2 18 . CS . M 1 . 18 bits address RWS O 2 19 -1 1 M = 2 20 I 2 19 20 bit address A . . CS M 2 2 additional bit to select one of . RWS O 2 19 +2 18 -1 the four 256 K x 32 RAM chips via decoder 2 19 +2 18 I . A . CS M3 . RWS 2 20 -1 O Output bus 8 8 DIGITAL DESIGN 101, University of California RTL Storage Components
Timer Counter Design a circuit that outputs a 1 every 60 clock cycles using an 8-bit up/down counter with a synchronous reset control input and other necessary logic gates. D E D Operations E Up/Down Counter 0 X No change 1 0 Count up Reset Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 1 1 Count down D 0 E 1 Up/Down Counter 60 is 00111100 Clk 0 0 1 1 1 1 0 0 Reset count when it reaches 60 by Reset Q7 Q3 Q6 Q5 Q4 Q2 Q1 Q0 setting Reset = 0 OUT 9 DIGITAL DESIGN 101, University of California RTL Storage Components
FIFO Timing Complete timing diagram for a FIFO queue. Assume all storage components (RAM and counters) contain 0s initially, Reset is always 1 and Enable is always 1. Clk IN 42 100 8 READ/WRITE OUT 10 DIGITAL DESIGN 101, University of California RTL Storage Components
FIFO Timing 45 Read/Write Enable Read/Write Enable Operations Operations X 0 X 0 No change No change 0 1 0 1 Read Read 1 1 1 1 Write Write empty empty empty empty Back empty 45 45 34 34 Reset 34 23 23 Front E E Back Front Reset Reset Clk 1 10 1 10 23 1 0 1023 empty Comparator S Selector 1022 empty Back < = > 1021 data 1K RAM . . . A Enable CS Read/ write RWS data data Front 2 I/O b empty 1 Emp 0 Full 11 DIGITAL DESIGN 101, University of California RTL Storage Components
FIFO queue implemented with a 1K RAM Clk First in , first out IN 42 100 8 Counters update at clk’s positive READ/ edge WRITE OUT 8 42 100 t t Reset E E Front Back Reset Reset Clk 1 10 1 10 Read/Write Enable Read/Write Enable Operations Operations X 0 X 0 No change No change 1 0 0 1 0 1 Read Read Comparator S Selector 1 1 1 1 Write Write < = > 1K RAM A Enable CS Read/ RWS write I/O bus Empty Full 12 12 DIGITAL DESIGN 101, University of California RTL Storage Components
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