Chapter 7 Clocking Dynamic Latches Registers Sequential Logic q - - PowerPoint PPT Presentation

1 Digital IC Design

Chapter 7 Sequential Logic q g

Overview

Static Latches Registers Static Latches Registers Clocking Dynamic Latches Registers

• C2MOS
• NORA
• TSPC

Sequential Logic

Registers Latches

Combinational

Latches Flip-flops

Logic State Comb. Logic State Comb. Logic State Comb. Logic State

Problem 7

VDD

B Y Z A

a) b)

B Q B B X B t A

a) Identify the circuit. b) Draw Euler path and sketch layout c) Draw Waveforms for X, Y, Z and Q

2

Problem 7 - Solution

VDD

B X Y Z

Y

b)

A B Q B B X

A B Q Z X

B A

c)

B t Q Z Y X

c)

h

Digital IC Design

Chapter 11 Arithmetic Building Blocks g

Binary Adder S A B = ⊕ Half Adder

A B

HA

Co

• C

AB S A B C = = ⊕ ⊕ = Full adder

S Ci A S B

FA

Co

• ABC

ABC ABC ABC C AB AC BC = + + + = + +

Ci A S B Co

Binary Adder Cell (Two’s Complement)

A B C i S C o 0 Delete

A B

HA

Co

0 Delete 1 1 0 Delete 1 1 0 Propagate 1 1 1 Propagate 1 1 0 Propagate 1 1 1 Propagate

S Ci A S B

FA

Co

1 1 1 Propagate 1 1 1 Generate 1 1 1 1 1 Generate

Ci A S B Co

3

Problem 4

Pi Pi+1 P G P G

a) What is the name and purpose f hi i ?

Ci+1 Cin Pi Carry

Sum

Gi Pi+1 Gi+1 Carry

Sum

• f this unit?

b) Draw the architecture of a 6-bit adder using this unit. c) Show longest path if A = 101011 and B = 100101

Si Si+1

d) Suggest simplification to first and last module.

Problem 4 - Solution

Bit # 5 4 3 2 1 A 1 1 1 1 B 1 1 1 Generate 1 1

Delete, Propagate, D A B P A B = = ⊕

P0 P1 Cin P0 Carry

Sum

G0 P1 G1 Carry

Sum

P2 P3 P2 Carry

Sum

G2 P3 G3 Carry

Sum

P4 P5 P4 Carry

Sum

G4 P5 G5 Carry

Sum Propagate 1 1 1 Delete 1

Generate, G AB =

Sum

S0 S1

Sum Sum

S2 S3

Sum Sum

S4 S5

Sum

Solution manual What I believe to be longest path!

Digital IC Design

Chapter 12 Memories

Problem 6

WL Q M4 M2 V dd

M RWL WWL WL BL BL M5 Q M1 M3 M6 Q M

1 3

BL2 C

S

M

2

BL1 BL C

S

M

1

a) Describe the functional difference between the three RAM cells. b) Describe a write-read cycle for each.

4

6-transistor SRAM Cell

WL

Vdd

Flip-Flop introduced in Chapter 7

BL BL M5 Q M1 M3 M6 M4 M2 Q

Vdd

Transistor sizing

BL BL

Transistor sizing important to ensure functionality

3 transistor DRAM Cell

WWL

BL1 VDD

Write cycle

M1 M3 CS M2 RWL X

W

X VDD-VT WWL

R

RWL

Read cycle

BL2 BL1 Read Write

Inversed Value is Read

BL2 VDD-VT ΔV

Restore of 1 transistor DRAM Cell

WL BL V(1)

VBL

M1 CS WL CBL Sense amp. activated VPre V(0)

ΔV(1) = small change

Destructive Read, needs restore! Feedback of sense amplifier output to BL Word line activated