Internal Memory Patrick Happ Raul Queiroz Feitosa
Objective To present a survey of semiconductor main memory technology. 2 Internal Memory
Outline Semiconductor Main Memory Flash Memory Random Access Memories – RAMs Advanced DRAM Organization Error Detection/Correction 3 Internal Memory
Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access Read-write Electrically, byte- Electrically Volatile memory (RAM) memory level Read-only Masks memory (ROM) Read-only Not possible memory Programmable ROM (PROM) Erasable PROM UV light, chip- (EPROM) level Nonvolatile Electrically Read-mostly Electrically, byte- (EEPROM) memory level Electrically, block- Flash memory level 4 Internal Memory 17/09/2020
Semiconductor Memory Types RAM PROM ROM EPROM FLASH EEPROM E2PROM 5 Internal Memory 17/09/2020
Memory Cell Operation 6 Internal Memory 17/09/2020
Read Only Memory (ROM) Permanent storage Nonvolatile Microprogramming (see later) Library subroutines Systems programs (BIOS) Function tables 7 Internal Memory 17/09/2020
Types of ROM Written during manufacture Very expensive for small runs Programmable (once) PROM Needs special equipment to program Read “mostly” Erasable Programmable (EPROM) Erased by UV Electrically Erasable (EEPROM) Takes much longer to write than read Flash memory Erase whole memory electrically 8 Internal Memory 17/09/2020
Outline Semiconductor Main Memory Flash Memory Random Access Memories – RAMs Advanced DRAM Organization Error Detection/Correction 9 Internal Memory
How a flash memory works A flash cell is a npn MOSFET with two gates: control and floating, separated by an isolating oxide layer. 10 Internal Memory 17/09/2020 Source: https://www.explainthatstuff.com/flashmemory.html
How a flash memory works To switch it “on”, a positive voltage is applied to the bit line and the word line. Electrons flow from the source to the drain. Some also bypass the oxide layer by a process called tunneling and get stuck in the floating gate. 11 Internal Memory 17/09/2020 Source: https://www.explainthatstuff.com/flashmemory.html
How a flash memory works To switch it back “off”, a negative voltage on the wordline, repels the electrons back the way they came, clearing the floating gate and making the transistorstore a zero again. An in-circuit wiring is used to apply the electric field either to the entire chip or to predetermined sections known as blocs. 12 Internal Memory 17/09/2020 Source: https://www.explainthatstuff.com/flashmemory.html
Outline Semiconductor Main Memory Flash Memory Random Access Memories – RAMs Advanced DRAM Organization Error Detection/Correction 13 Internal Memory
Random Access Memory RAM Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary storage Static or dynamic 14 Internal Memory 17/09/2020
Static RAM Bits stored as on/off switches No charges to leak No refreshing needed when powered More complex construction Larger per bit More expensive Faster Used to implement cache memory (seen in a later chapter) Digital → Uses flip-flops 15 Internal Memory 17/09/2020
Static RAM Structure state 1 state 1 state 0 on off off on high low Read low high Write applies value is on line B value to B and off on compliment to B on off 16 Internal Memory 17/09/2020
Dynamic RAM Bits stored as charge in capacitors Charges leak Need refreshing even when powered Simpler construction Smaller per bit Less expensive Need refresh circuits Slower Used to implement main memory Essentially analogue → Level of charge determines value 17 Internal Memory 17/09/2020
Dynamic RAM Structure Write Read charge fed charge through transfered line to to capacitor sensor 0/1 0/1 on on 18 Internal Memory 17/09/2020
Refreshing Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance 19 Internal Memory 17/09/2020
SRAM vs. DRAM Both volatile Power needed to preserve data Dynamic cell Simpler to build, smaller More dense Less expensive Needs refresh Larger memory units Static Faster Cache 20 Internal Memory 17/09/2020
Typical 16 Mb DRAM (4M x 4) 21 Internal Memory 17/09/2020
Simplified DRAM Read Timing 22 Internal Memory 17/09/2020
Packaging 23 Internal Memory 17/09/2020
Module Organization Example 1: a 256K 8 bit word organization 24 Internal Memory 17/09/2020
Module Organization Example 1: a 1M 8 bit word organization 25 Internal Memory 17/09/2020
Outline Semiconductor Main Memory Flash Memory Random Access Memories – RAMs Advanced DRAM Organization Error Detection/Correction 26 Internal Memory
Advanced DRAM Organization Basic DRAM same since 70’s. Enhanced DRAM Contains small SRAM as well SRAM holds last line read (c.f. Cache!) 27 Internal Memory 17/09/2020
Synchronous DRAM (SDRAM) Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle (leading & trailing edge) 28 Internal Memory 17/09/2020
SDRAM Read Timing valid valid valid valid data data data data 29 Internal Memory 17/09/2020
DDR SDRAM SDRAM can only send data once per clock Double-data-rate SDRAM can send data twice per clock cycle Rising edge and falling edge 30 Internal Memory 17/09/2020
DDR SDRAM - Read Timing 31 Internal Memory 17/09/2020
DDR Generations By increasing the operational frequency and the prefetch buffer from 2 to 4 and to 8 bits higher data rates were achieved DDR SDRAM Bus clock Internal rate Prefetch Transfer Rate First Standard (MHz) (MHz) (min burst) (MT/s) release DDR 100 – 200 100 – 200 2n 200 – 400 2000 200 – 533 100 – 266 4n 400 – 1066 2004 DDR2 DDR3 400 – 1066 100 – 266 8n 800 – 2133 2007 DDR4 1066 – 2133 133 – 266 8n 2133 – 4266 2011 ? DDR5 Specifications released in July 2020 32
Outline Semiconductor Main Memory Flash Memory Random Access Memories – RAMs Advanced DRAM Organization Error Detection/Correction 33 Internal Memory
Error Correction Hard Failure Permanent defect Soft Error Random, non-destructive No permanent damage to memory Detected using Hamming error correcting code 34 Internal Memory 17/09/2020
Error Correcting Code Function 35 Internal Memory 17/09/2020
Text Book References Stallings 11 th edition, chapter 6 36 Internal Memory 17/09/2020
Internal Memory END 37 Internal Memory 17/09/2020
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