Internal Memory Patrick Happ Raul Queiroz Feitosa Objective To - - PowerPoint PPT Presentation

Internal Memory

Patrick Happ Raul Queiroz Feitosa

Objective

To present a survey of semiconductor main memory technology.

Outline

 Semiconductor Main Memory  Flash Memory  Random Access Memories – RAMs  Advanced DRAM Organization  Error Detection/Correction

Semiconductor Memory Types

Semiconductor Memory Types

RAM ROM PROM EPROM EEPROM E2PROM FLASH

Memory Cell Operation

Read Only Memory (ROM)

 Permanent storage

Nonvolatile

 Microprogramming (see later)  Library subroutines  Systems programs (BIOS)  Function tables

Types of ROM

Written during manufacture

 Very expensive for small runs

Programmable (once)

 PROM  Needs special equipment to program

Read “mostly”

 Erasable Programmable (EPROM)

 Electrically Erasable (EEPROM)

 Flash memory

Outline

 Semiconductor Main Memory  Flash Memory  Random Access Memories – RAMs  Advanced DRAM Organization  Error Detection/Correction

How a flash memory works

A flash cell is a npn MOSFET with two gates: control and floating, separated by an isolating oxide layer.

How a flash memory works

To switch it “on”, a positive voltage is applied to the bit line and the word line. Electrons flow from the source to the drain. Some also bypass the oxide layer by a process called tunneling and get stuck in the floating gate.

To switch it back “off”, a negative voltage on the wordline, repels the electrons back the way they came, clearing the floating gate and making the transistorstore a zero again. An in-circuit wiring is used to apply the electric field either to the entire chip or to predetermined sections known as blocs.

How a flash memory works

Outline

 Semiconductor Main Memory  Flash Memory  Random Access Memories – RAMs  Advanced DRAM Organization  Error Detection/Correction

Misnamed as all semiconductor memory is random

access

Read/Write Volatile Temporary storage Static or dynamic

Random Access Memory RAM

Static RAM

 Bits stored as on/off switches  No charges to leak  No refreshing needed when powered  More complex construction  Larger per bit  More expensive  Faster  Used to implement cache memory (seen in a later chapter)  Digital→ Uses flip-flops

Static RAM Structure

high low

• ff
• ff
• n
• n

state 1 state 1 low high

• n
• n
• ff
• ff

state 0 Read value is on line B Write applies value to B and compliment to B

Dynamic RAM

 Bits stored as charge in capacitors  Charges leak  Need refreshing even when powered  Simpler construction  Smaller per bit  Less expensive  Need refresh circuits  Slower  Used to implement main memory  Essentially analogue → Level of charge determines value

Dynamic RAM Structure

0/1

• n

charge transfered to capacitor Write 0/1

• n

charge fed through line to sensor Read

Refreshing

Refresh circuit included on chip Disable chip Count through rows Read & Write back Takes time Slows down apparent performance

SRAM vs. DRAM

Both volatile

 Power needed to preserve data

Dynamic cell

 Simpler to build, smaller  More dense  Less expensive  Needs refresh  Larger memory units

Static

 Faster  Cache

Typical 16 Mb DRAM (4M x 4)

Simplified DRAM Read Timing

Packaging

Module Organization

Example 1: a 256K 8 bit word organization

Module Organization

Example 1: a 1M 8 bit word organization

Outline

 Semiconductor Main Memory  Flash Memory  Random Access Memories – RAMs  Advanced DRAM Organization  Error Detection/Correction

Advanced DRAM Organization

 Basic DRAM same since 70’s.  Enhanced DRAM

Contains small SRAM as well SRAM holds last line read (c.f. Cache!)

Synchronous DRAM (SDRAM)

 Access is synchronized with an external clock  Address is presented to RAM  RAM finds data (CPU waits in conventional DRAM)  Since SDRAM moves data in time with system clock, CPU

knows when data will be ready

 CPU does not have to wait, it can do something else  Burst mode allows SDRAM to set up stream of data and fire

it out in block

 DDR-SDRAM sends data twice per clock cycle (leading &

trailing edge)

SDRAM Read Timing

DDR SDRAM

 SDRAM can only send data once per clock  Double-data-rate SDRAM can send data

twice per clock cycle

Rising edge and falling edge

DDR SDRAM - Read Timing

DDR Generations

By increasing the operational frequency and the prefetch buffer from 2 to 4 and to 8 bits higher data rates were achieved

DDR SDRAM Standard Bus clock (MHz) Internal rate (MHz) Prefetch (min burst) Transfer Rate (MT/s) First release

Outline

 Semiconductor Main Memory  Flash Memory  Random Access Memories – RAMs  Advanced DRAM Organization  Error Detection/Correction

Error Correction

 Hard Failure

Permanent defect

 Soft Error

Random, non-destructive No permanent damage to memory

 Detected using Hamming error correcting

code

Error Correcting Code Function

Text Book References

Stallings 11th edition, chapter 6

Internal Memory

END