Chapter 7 Clocking Dynamic Latches Registers Sequential Logic q - - PowerPoint PPT Presentation

1 Digital IC-Design

Chapter 7 Sequential Logic q g

Overview

Static Latches Registers Static Latches Registers Clocking Dynamic Latches Registers

• C2MOS
• NORA
• TSPC

Sequential Logic

Registers Latches

Combinational

Latches Flip-flops

Logic State Comb. Logic State Comb. Logic State Comb. Logic State

Register: Edge Triggered

Latch versus Register

Latch: Level Sensitive

Clk

D Clk Q

Latch

Clk

Register

D Clk Q

D Q D Q

Q on Clock Edge Q on Data

2

Clock Non-Idealities

Clock skew

Spatial a iation in tempo all eq i alent Spatial variation in temporally equivalent clock edges

Clock jitter

Temporal variations in consecutive edges of the clock signal the clock signal

Clock Non-Idealities

Both skew and jitter affects the cycle time Skew might lead to race through the registers Same clock at two

tskew tjitter

different parts of the chip

Clock Non-Idealities - Feedthrough

Clock feedthrough

VDD

Φ

0,5 1,5 2,5

Q

A C B Q

Φ

• 0,5

0,5 1

Time, ns

Clock feedthrough

Φ

Coupling in dynamic devices can lift the output

Example – Clock System

VDD (Always on)

Module 1 Global Clock Module 2

Data De- skew Enable 2 Enable 3 Phase Locked Loop

N

System Clock

CLK

f

SYS CLK

N f f M = ×

Local Clock Signals Module 3

N M On-Chip Clock Generation Clock Gating Clocked Modules

3

Latches

SR-latch (00 not allowed) JK-latch (all inputs allowed)

S CLK Q

JK latch (all inputs allowed) D-latch most important in CMOS sequential Circuits. D-latch realized with a

R CLK Q D CLK Q

D-latch realized with a relatively small number of transistors

CLK Q

Latches – Cells with Memory Static

Positive Feedback

Dynamic

"0" "1"

Dynamic

Often in DSP ASICs with continuous “refresh”

"1" "0"

Capacitive Storage

Static Latch 1

φ

Weak inv. D Q Q

8 Transistor D-latch using weak devices

φ

Weak inv. D Q Q

φ φ

Static Latch 2

φ φ φ

Positive Feedback

8 Transistor D-latch using transmission

D

φ φ

Q Q

φ

gates

D

φ φ

Q

φ

Q

4

Static Latch 3

φ φ

D Q Q

10 Transistor D-latch using clocked inverters

φ φ φ φ

Q

inverters

D Q Q

φ φ

SRAM Cell (Cross-Coupled Inverters)

Word Select

Open during read/ write

Q Q

Dynamic Latches D-latch using capacitor storage

φ

D Q Q

φ

capacitor storage The parasitic capacitance is

D Q

φ φ

• ften enough

Q

φ

Charge Sharing Charge sharing

D Q

φ φ

Good Design Charge sharing when the inner transistors switch

φ

Q

φ

Q D Q Q

φ

D

φ Discharged during high Φ

5

Race Problem

D Q

Signal race when the latch is open

φ

D Q Q Q

φ

Register: Master-Slave Latches

φ

D Q

φ

D Q Q X

φ

D=1

The Master- Slave register is not signal transparent

φ φ φ1 φ1 φ2 φ2

X Q

Testing the Functionality of the Logic

A long pipelined chain with combinatorial logic

An enormous amount of test vectors will be needed egister

Combina- tional

egister

Combina- tional

egister Feedback makes the problem even worse Re Re Re

Test patterns in parallel?

Serial Scan-based Test – Two Modes

Scan in (serial) Parallel Parallel

Register

Combina- tional N N

Register

Combina- tional N N

Register

N N Scan out in

• ut

Scan mode - serial shift registers

(serial)

Normal mode - N-bit wide registers

6

Test Test IN0 Test Test IN1 Test Test IN2 Test Test IN3 Scan Scan

Scan Register Based Test

Latch

OUT0

Latch

OUT1

Latch

OUT2

Latch

OUT3 Out In

TEST

= normal

N cycles

= scan

1 cycle Φ1 Φ2 Scan chain of N clock cycles in test sequence

Serial-Parallel Register

MUX or Pass

REG C ll REG C ll Serial Out Serial In

Transistors

Combinational Logic

Cell REG Cell Cell REG Cell Parallel I nput Parallel Output

Normal mode Parallel d

C

REG Cell REG Cell

Scan mode Serial and Parallel

N serial cycles

Scan Register Based Test

1 cycle to evaluate logic N serial cycles

mbinational Logic

REG Cell REG Cell REG Cell REG Cell

mbinational Logic

REG Cell REG Cell REG Cell REG Cell

mbinational Logic

REG Cell REG Cell REG Cell REG Cell

Com

REG Cell REG Cell

Com

REG Cell REG Cell

Com

REG Cell REG Cell REG[0] REG[1] SCANIN A B

Scan Test in a Datapath

Partial Scan

REG[4] REG[3] REG[2] + COMPIN

Partial Scan

REG[5] COMP OUT SCANOUT

7

Clocking

True single phase clocking (TSPC) Two phase Pseudo four phase, safe and slow Overlapping Overlapping Non-overlapping

Two-Phase Clocking

Non-overlapping Overlapping

Ext. CLK

φ1 φ2 φ

Ext. CLK

φ2 φ1 φ

1 1 1 1

φ1 φ2 φ1 φ2

Non-overlap Overlap

Pseudo Four-Phase Clocking

Safe and Slow L ge Clo k B Large Clock Bus

Ext. CLK

φ1 φ2 φ1 φ1 φ2 φ φ2

2

φ2 φ1

Single-Phase Clocking

Two phases but only one clock wire φ φ

Cell (Reg)

φ φ

Cell (Reg)

φ φ

Cell (Reg)

φ φ

Cell (Reg)

Clock Wire

φ φ φ φ φ φ φ φ

8

Static Registers

φ φ1 φ φ2

Four clock phases

D Q

φ1 φ1 φ1 φ2 φ2 φ2 φ1 φ2

p

D Q

φ2 φ1

Dynamic Register: C2MOS

Out In

φ φ φ φ

C2MOS: Pipelining

Out In

φ φ φ φ

Non- inverting logic Non- inverting logic

φ φ

Overlapping clock allowed if non-inverting logic C2MOS: Overlapping Clock

Out

In=1

φ φ

Closed

Out

In=0

φ φ

Out

φ φ φ

Out

φ φ φ

Closed

φ φ

Transparent register if inverting logic

9

C2MOS: Overlapping Clock

Closed

Out

In=1

φ φ φ φ φ

Closed Closed

Out

In=0

φ φ φ φ φ

Closed

φ φ φ φ

NORA (NO RAce)

Combinational Combinational Latch Latch φ φ

PDN PUN

φ φ φ φ φ φ

PDN PUN

φ φ φ φ

Combines np-logic and C2MOS

φ Module: Precharge on φ =1 φ Module: Precharge on φ =0

True Single Phase Clocking (TSPC)

N-Block P-Block

φ φ

In

φ

OutN

φ φ φ

OutP

In

φ

OutN

φ φ φ

OutP

φ φ

True Single Phase Clocking (TSPC)

N-Block P-Block

From P-Blocks PUN PDN

φ

OutN

φ φ φ φ φ

To N-Blocks From other N-Blocks

φ φ

10

TSPC Reliability

The clock edge must be sharp to avoid transparency

I

OutN

X

sharp to avoid transparency when the signal comes from the previous block

φ φ

In

φ

OutN

φ

X

Both N-MOS are conducting

In X In X

TSPC Reliability

φ φ

In

OutN

N N P P

φ φ φ φ φ φ

OutP

φ φ

N N P P

φ φ

CLK

OK

φ φ

OutP

In

OutN

φ φ φ φ φ φ

CLK

OK