[PPT] - ECE 550D Fundamentals of Computer Systems and Engineering Fall 2016 PowerPoint Presentation

SLIDE 1

ECE 550D

Fundamentals of Computer Systems and Engineering

Fall 2016

Storage and Clocking

Tyler Bletsch Duke University Slides are derived from work by Andrew Hilton (Duke)

SLIDE 2

2

VHDL: Behavioral vs Structural

A few words about VHDL
Structural:
Spell out at (roughly) gate level
Abstract piece into entities for abstraction/re-use
Very easy to understand what synthesis does to it
Behavioral:
Spell out at higher level
Sequential statements, for loops, process blocks
Can be difficult to understand how it synthesizes
Difficult to resolve performance issues

SLIDE 3

3

Last time…

Who can remind us what we did last time?
Add
Substract
Bit shift
Floating point

SLIDE 4

4

So far…

We can make logic to compute “math”
Add, subtract,… (we’ll see multiply/divide later)
Bitwise: AND, OR, NOT,…
Shifts
Selection (MUX)
…pretty much anything
But processors need state (hold value)
Registers
…

SLIDE 5

5

Memory Elements

All the circuits we looked at so far are combinational circuits:

the output is a Boolean function of the inputs.

We need circuits that can remember values (registers,

memory)

The output of the circuit is a function of the input and a

function of a stored value (state)

Circuits with storage are called sequential circuits
Key to storage: feedback loops from outputs to inputs

SLIDE 6

6

Ideal Storage – Where We’re Headed

Ultimately, we want something that can hold 1 bit and we

want to control when it is re-written

However, instead of just giving it to you as a magic black box,

we’re going to first dig a bit into the box

“flip flop” = device that holds one bit (0 or 1) bit to be written bit currently being held bit to control when we write

SLIDE 7

7

Building up to the D Flip-Flop and beyond

SR Latch

Q Q R S D E Q Q R S

D Latch

D latch

D Q E Q

D latch

D Q E

D latch

D Q E !Q !Q Q D C

DFF

D Q E Q

D Flip-Flop

32 bit reg

D Q E Q

Register

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

(too awkward) (bad timing) (okay but only one bit) (nice!)

SLIDE 8

8

FF Step #1: NOR-based Set-Reset (SR) Latch

R S Q Q 1 1 R S Q Q 1 1

R S Q 0 0 Q 0 1 1 1 0 0 1 1 -

Don’t set both S & R to 1. Seriously, don’t do it.

SLIDE 9

9

R S Q Q 1 1 R S Q Q 1 1 1

Set-Reset Latch (Continued)

Time S 0

1

R

1

Q

1

SLIDE 10

10

R S Q Q 1 1 R S Q Q 1 1 1

Set-Reset Latch (Continued)

Time S 0

1

R

1

Q

1

Set Signal Goes High Output Signal Goes High

SLIDE 11

11

R S Q Q 1 1 R S Q Q 1 1 1

Set-Reset Latch (Continued)

Time S 0

1

R

1

Q

1

Set Signal Goes Low Output Signal Stays High

SLIDE 12

12

R S Q Q 1 1 R S Q Q 1 1 1

Set-Reset Latch (Continued)

Time S 0

1

R

1

Q

1

Until Reset Signal Goes High Then Output Signal Goes Low

SLIDE 13

13

SR Latch

Downside: S and R at once = chaos
Downside: Bad interface
So let’s build on it to do better

SLIDE 14

14

Building up to the D Flip-Flop and beyond

SR Latch

Q Q R S D E Q Q R S

D Latch

D latch

D Q E Q

D latch

D Q E

D latch

D Q E !Q !Q Q D C

DFF

D Q E Q

D Flip-Flop

32 bit reg

D Q E Q

Register

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

(too awkward) (bad timing) (okay but only one bit) (nice!)

SLIDE 15

15

FF Step #2: Data Latch (“D Latch”)

Starting with SR Latch

Q Q R S

SLIDE 16

16

Data Latch (D Latch)

Starting with SR Latch Change interface to Data + Enable (D + E) If E=0, then R=S=0. If E=1, then S=D and R=!D

Data Enable Q Q R S

SLIDE 17

17

Data Latch (D Latch)

Data Enable Q Q

D E Q 0 1 0 1 1 1

0 Q

Time D 0

1

E

1

Q

1

E goes high D “latched” Stays as output R S

SLIDE 18

18

Data Latch (D Latch)

Data Enable Q Q

D E Q 0 1 0 1 1 1

0 Q

Time D 0

1

E

1

Q

1

Does not affect Output E goes low Output unchanged By changes to D R S

SLIDE 19

19

Data Latch (D Latch)

Data Enable Q Q

D E Q 0 1 0 1 1 1

0 Q

Time D 0

1

E

1

Q

1

E goes high D “latched” Becomes new output R S

SLIDE 20

20

Data Latch (D Latch)

Data Enable Q Q

D E Q 0 1 0 1 1 1

0 Q

Time D 0

1

E

1

Q

1

Slight Delay (Logic gates take time) R S

SLIDE 21

21

Logic Takes Time

Logic takes time:
Gate delays: delay to switch each gate
Wire delays: delay for signal to travel down wire
Other factors (not going into them here)
Need to make sure that signals timing is right
Don’t want to have races or wacky conditions..

SLIDE 22

22

Clocks

Processors have a clock:
Alternates 0 1 0 1
Like the processor’s internal metronome
Latch  logic  latch in one clock cycle
3.4 GHz processor = 3.4 Billion clock cycles/sec

One clock cycle

SLIDE 23

23

FF Step #3: Using Level-Triggered D Latches

First thoughts: Level Triggered
Latch enabled when clock is high
Hold value when clock is low

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 24

24

Strawman: Level Triggered

How we’d like this to work
Clock is low, all values stable

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

010 111 100 001

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 25

25

Strawman: Level Triggered

How we’d like this to work
Clock goes high, latches capture and xmit new val

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

010 010 100 100

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 26

26

Strawman: Level Triggered

How we’d like this to work
Signals work their way through logic w/ high clk

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

010 010 100 100

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 27

27

Strawman: Level Triggered

How we’d like this to work
Clock goes low before signals reach next latch

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

010 010 100 100

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 28

28

Strawman: Level Triggered

How we’d like this to work
Clock goes low before signals reach next latch

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

111 010 000 100

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 29

29

Strawman: Level Triggered

How we’d like this to work
Everything stable before clk goes high

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

111 010 000 100

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 30

30

Strawman: Level Triggered

How we’d like this to work
Clk goes high again, repeat

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

111 111 000 000

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 31

31

Strawman: Level Triggered

Problem: What if signal reaches latch too early?
I.e., while clk is still high

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

111 111 101 000

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 32

32

Strawman: Level Triggered

Problem: What if signal reaches latch too early?
Signal goes right through latch, into next stage..

D latch

D Q E Q

D latch

D Q E Q

Logic

Clk

3 3

111 111 101 101

Clk

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 33

33

That would be bad…

Getting into a stage too early is bad
Something else is going on there  corrupted
Also may be a loop with one latch
Consider incrementing counter (or PC)
Too fast: increment twice? Eeek…

D latch

D Q E Q

+1

3

001 010

This slide describes how D-latches can malfunction because they were level triggered. Real D-flip-flops are edge-triggered, and we’re showing you why that’s important.

SLIDE 34

34

Building up to the D Flip-Flop and beyond

SR Latch

Q Q R S D E Q Q R S

D Latch

D latch

D Q E Q

D latch

D Q E

D latch

D Q E !Q !Q Q D C

DFF

D Q E Q

D Flip-Flop

32 bit reg

D Q E Q

Register

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

(too awkward) (bad timing) (okay but only one bit) (nice!)

SLIDE 35

35

FF Step #4: Edge Triggered

Instead of level triggered
Latch a new value at a clock level (high or low)
We use edge triggered
Latch a value at an clock edge (rising or falling)

Falling Edges Rising Edges

SLIDE 36

36

Our Ultimate Goal: D Flip-Flop

Rising edge triggered D Flip-flop
Two D Latches w/ opposite clking of enables

D latch

D Q E

D latch

D Q E Q Q Q D C

SLIDE 37

37

D Flip-Flop

Rising edge triggered D Flip-flop
Two D Latches w/ opposite clking of enables
On Low Clk, first latch enabled (propagates value)
Second not enabled, maintains value

D latch

D Q E

D latch

D Q E Q Q Q D C

SLIDE 38

38

D Flip-Flop

Rising edge triggered D Flip-flop
Two D Latches w/ opposite clking of enables
On Low Clk, first latch enabled (propagates value)
Second not enabled, maintains value
On High Clk, second latch enabled
First latch not enabled, maintains value

D latch

D Q E

D latch

D Q E Q Q Q D C

SLIDE 39

39

D Flip-Flop

No possibility of “races” anymore
Even if I put 2 DFFs back-to-back…
By the time signal gets through 2nd latch of 1st DFF

1st latch of 2nd DFF is disabled

Still must ensure signals reach DFF before clk rises
Important concern in logic design “making timing”

D latch

D Q E

D latch

D Q E Q D C

D latch

D Q E

D latch

D Q E Q C

SLIDE 40

40

Making Timing

Making timing is important in a design
If you don’t make timing, your logic won’t compute right
Synthesis tool (Quartus) tells you what max freq
Running above this your logic doesnt “finish” in time

SLIDE 41

41

D Flip-flops (continued…)

Could also do falling edge triggered
Switch which latch has NOT on clk
D Flip-flop is ubiquitous
Typically people just say “latch” and mean DFF
Which edge: doesn’t matter
As long as consistent in entire design
We’ll use rising edge

SLIDE 42

42

D flip flops

Generally don’t draw clk input
Have one global clk, assume it goes there
Often see > as symbol meaning clk
Maybe have explicit enable
Might not want to write every cycle
If no enable signal shown, implies always enabled
Get output and NOT(output) for “free”

DFF

D Q E Q

DFF

D Q Q

DFF

D Q > Q

SLIDE 43

43

DFFs in VHDL

x: dffe port map ( clk => clk, --the clock d => someInput, --the input is d q => theOutput, --the output is q ena => en, --the enable clrn => '1', --clear prn => '1'); --set Also, comes in “dff” with no enable

SLIDE 44

44

A word of advice

signal x_q : std_logic; signal x_d: std_logic; x : dffe port map (…, d=> x_d, q=>x_q,…);

Use naming convention: x_d, x_q
Write x_d, read x_q
Remember new value shows up next cycle

x x_d x_q

SLIDE 45

45

A few words about timing

Homework 2: VGA Controller
Requires certain clock frequency
Else won’t control monitor properly
Quartus will tell you what timing you make
Fmax : how fast can this be clocked
Tells you your worst timing paths
From which dff to which dff
Can see in schematic viewer (usually)
Homework 2
Should be plenty of slack
But if not…

SLIDE 46

46

Fixing timing misses

Typical approach: reduce logic (gate delays)
Better adder?
Rethink approach?
Change “don’t care” behavior?
Fix high fanout
Duplicate high FO/simple logic
Also, feel free to ask for help from me/TAs
Quartus’s tools to help you fix them aren’t the best

SLIDE 47

47

Building up to the D Flip-Flop and beyond

SR Latch

Q Q R S D E Q Q R S

D Latch

D latch

D Q E Q

D latch

D Q E

D latch

D Q E !Q !Q Q D C

DFF

D Q E Q

D Flip-Flop

32 bit reg

D Q E Q

Register

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

(too awkward) (bad timing) (okay but only one bit) (nice!)

SLIDE 48

48

Stick a bunch of DFFs together to make a register

32 bit reg

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q in0 in1 in2 in31

. . .

ut0
ut1
ut2
ut31

enable

SLIDE 49

49

Next evolution: multiple registers

32 bit reg

D Q E Q

Register

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

DFF

D Q E Q

(nice!)

En0 En1 En30 En31

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q WrData En0 En1 En30 En31

…

Register File

(Tremendous!)

SLIDE 50

50

Register File

Can store one value… How about many?
Register File
In processor, holds values it computes on
MIPS, 32 32-bit registers
How do we build a Register File using D Flip-Flops?
What other components do we need?

SLIDE 51

51

Register File: Interface

4 inputs
3 register numbers (5 bit): 2 read, 1 write
1 register write value (32 bits)
2 outputs
2 register values (32 bits)

Register File rnumA rnumB rnumW Wval Aval Bval

SLIDE 52

52

Register file strawman

Use a mux to pick read ?
32 input mux = slow
(other regs not pictured)

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

… …

SLIDE 53

53

Register File Design

Two problems: write and read
Writing the registers
Need to pick which reg
Have reg num (e.g., 19)
Need to make En19=1
En0, En1,… = 0
Read: Use a mux to pick?
32-input mux = slow
Need a better method…
Let’s talk about writing first.

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

… …

WrData En0 En1 En30 En31

SLIDE 54

54

First: A Decoder

First task: convert binary number to “one hot”
Saw this before
Take register number

Decoder

3 101

1

SLIDE 55

55

Register File

Now we know how to write:
Use decoder to convert reg # to one hot
Send write data to all regs
Use one hot encoding of reg # to enable right reg
Still need to fix read side
32 input mux (the way we’ve made it) not realistic
To do this: expand our world from {1,0} to {1, 0, Z}

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q WrData En0 En1 En30 En31

…

SLIDE 56

56

Kind of like water in a pipe…

To understand Z, let’s make an analogy
Think of a wire as a pipe
Has water = 1
Has water = 0
This wire is 0 (it has no water)

SLIDE 57

57

Kind of like water in a pipe…

To understand Z, let’s make an analogy
Think of a wire as a pipe
Has water = 1
Has water = 0
This wire is 1 (it is full of water)

SLIDE 58

58

Kind of like water in a pipe…

To understand Z, let’s make an analogy
Think of a wire as a pipe
Has water = 1
Has water = 0
Suppose a gate drives a 0 onto this wire
Think of it as sucking the water out

SLIDE 59

59

Kind of like water in a pipe…

To understand Z, let’s make an analogy
Think of a wire as a pipe
Has water = 1
Has water = 0
Suppose the gate now drives a 1
Think of it as pumping water in

1

SLIDE 60

60

So this third option: Z

There is a third possibility: Z (“high impedance”)
Neither pushing water in, nor sucking it out
Just closed off/blocked
Prevents electricity from flowing through
Gate that gives us Z : Tri-state

D E Q 0 1 0 1 1 1

0 Z

D Q E

SLIDE 61

61

CMOS: Complementary MOS

2 inputs: E and D. What does this do?
Write truth table for output

Vcc Gnd

E Output E D

E D Output 1 1 1 1

SLIDE 62

62

CMOS: Complementary MOS

2 inputs: E and D. What does this do?
Write truth table for output
When E =1, straightforward

Vcc Gnd

E Output E D

E D Output 1 1 0 1 1 1 0

SLIDE 63

63

CMOS: Complementary MOS

2 inputs: E and D. What does this do?
Write truth table for output
When E =1, straightforward
When E= 0, no connection: Z

Vcc Gnd

E Output E D

E D Output 0 Z 1 Z 1 0 1 1 1 0

SLIDE 64

64

High Impedance: Z

Z = High Impedance
No path to power or ground
“Gate” does not produce a 1 or a 0
Previous slide: tri-state inverter
More commonly drawn: tri-state buffer
E = enable, D = data

D E Out 0 1 0 1 1 1 X 0 Z D Out E

X=“Don’t care”

SLIDE 65

65

Remember this rule?

Remember I told you not to connect two outputs?
If one gate tries to drive a 1 and the other drives a 0
One pumps water in.. The other sucks it out
Except its electric charge, not water
“Short circuit”—lots of current -> lots of heat

a b c d BAD!

SLIDE 66

66

We’ve had this rule one day… and you break it

It’s ok to connect multiple outputs together Under one circumstance: All but one must be outputting Z at any time

D0 E0 D1 E1 Dn-2 En-2 Dn-1 En-1

SLIDE 67

67

Mux, implemented with tri-states

We can build effectively a mux

from tri-states

Much more efficient for large #s of

inputs (e.g., 32)

Decoder

5 11110

1

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

… … … …

SLIDE 68

68 En0 En1 En30 En31

Register File

Now we can write and read in one clock cycle!

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q

32 bit reg

D Q E Q WrData En0 En1 En30 En31

…

SLIDE 69

69

Ports

What we just saw: read port
Ability to do one read / clock cycle
May want more: read 2 source registers per instr
Maybe even more if we do many instrs at once
This design: can just replicate port
Another decoder
Another set of tri-states
Another output bus (wire connecting the tri-states)
Earlier: write port
Ability to do one write/cycle
Could add more: need muxes to pick wr values

SLIDE 70

70

Minor Detail

FYI: This is not how a register file is implemented
(Though it is how other things are implemented)
Actually done with SRAM
We’ll see how those work soon