Asynchronous sequence circuits • An asynchronous sequence machine is a sequence circuit without flip-flops • Asynchronous sequence machines are based on combinational gates with feedback Upon analysis it is assumed : Only one signal at a time in the gate circuit can change its value at any time William Sandqvist william@kth.se
Golden rule William Sandqvist william@kth.se
Asynchronous state machine Asynchronous state machines are used when it is necessary to maintain a state, but when there is no clock available. • All flip-flops and latches are themselfes asynchronous state machines • They are useful to synchronize events in situations where metastability is/can be a problem William Sandqvist william@kth.se
SR-latch with NOR-gates To analyze the behavior of an asynchronous circuit one assumes ideal gates and summarizes all the delay to a single block with delay Δ . ideal gates (delay = 0) Delay R Y y Q S William Sandqvist william@kth.se
Analys av det asynkrona sekvensnätet Genom att vi har ett fördröjningsblock kan vi betrakta y som nuvarande tillstånd Y som nästa tillstånd R Y y Q S William Sandqvist william@kth.se
State function Thus, we can develop a functional relationship of the next state Y depending on the input signals S and R and the current state y R Y y Q S = + + ( ) Y R S y William Sandqvist william@kth.se
BV uses State table binary code = + + From statefunction to ( ) Y R S y truth table Next state Present = + + ( ) y S R Y R S y state SR = 00 01 10 11 = + + 0 0 0 0 0 ( 0 0 ) y = + + Y Y Y Y 0 0 1 0 1 ( 0 0 ) = + + 0 1 0 1 1 ( 1 0 ) 0 0 0 1 0 = + + 0 1 1 0 1 ( 1 0 ) 1 1 0 1 0 = + + 1 0 0 1 0 ( 0 1 ) = + + 1 0 1 0 1 ( 0 1 ) Or, as in the exercise - using the = + + 1 1 0 1 0 ( 1 1 ) Karnaugh map … = + + 1 1 1 0 1 ( 1 1 ) William Sandqvist william@kth.se
( Exercise SR analysis ) + = + + = ⋅ + = ⋅ + = + ( ) ( ) Q R S Q R S Q R S Q S R R Q Next state Q + Present state Q Input signals SR 00 01 11 10 0 0 0 0 1 1 1 0 0 1 For binary order William Sandqvist william@kth.se
Stable states Next state Present state SR = 00 01 10 11 y Y Y Y Y 0 0 0 1 0 1 1 0 1 0 • Since we do not have flip-flops, but only combinational circuits, a state change can result in additional state changes • A state is Y = – stable if Y ( t ) = y ( t + Δ ) y stable – unstable if Y ( t ) ≠ y( t + Δ ) William Sandqvist william@kth.se
Exitation table The asynchronous coded state table is called Excitationstable The stable states (those with next state = present state) will be ”encircled” Next state Present state SR = 00 01 10 11 y Y Y Y Y Y = y 0 0 0 1 0 1 1 0 1 0 William Sandqvist william@kth.se
Terminology When dealing with asynchronous sequential circuits a different terminology is used • The synchronous uncoded state table is called flow table William Sandqvist william@kth.se
Flowtable and Statediagram (Moore) Next state Present Output Q state SR = 00 01 10 11 A A A B A 0 B B A B A 1 SR 10 00 00 ⁄ ⁄ 01 A 0 B 1 10 11 01 11 William Sandqvist william@kth.se
Flowtable and Statediagram (Mealy) Next state Output, Q Present state SR = 00 01 10 11 00 01 10 11 – A A A B A 0 0 0 – – B B A B A 1 1 SR/Q 10/ – 1 ? 1 ? 00/0 00/1 01/0 A B 10/1 11/0 0 ? 0 ? ⁄ 01 – ⁄ 11 – Don’t care (‘-’) has been selected for the output decoder. It does not matter if the output is changed before or after the state transition (= simpler gate array). William Sandqvist william@kth.se
Asynchronous Moore compatible • Asynchronous sequential circuits have similar structure as synchronous sequential circuits • Instead of flip-flops one have a "delay block" William Sandqvist william@kth.se
Asynchronous Mealy compatible • Asynchronous sequential circuits have similar structure as synchronous sequential circuits • Instead of flip-flops one have a "delay block" William Sandqvist william@kth.se
Analysis of asynchronous circuits The analysis is done in the following steps : 1) Replace the feedbacks in the circuit with delay element ∆ i . Input signal to delay-element forms the next state Y i , while the output signal y i represents the present state. 2) Find out the next-state and output expressions 3) Set up the corresponding excitationstable 4) Create a flow table by replacing the encoded states by symbolic states 5) Draw a state diagram if needed William Sandqvist william@kth.se
First: D-latch state function y D 1D Q Q Y Q D C1 C C = / C follow latch D-latch statefunction. Functional relationship between the current state y and next state Y = ⋅ + ⋅ Y D C y C follow latch William Sandqvist william@kth.se
Exemple: Master-Slave-flip-flop Master-slave D flip-flop is constructed from two asynchronous D-latches. Master Slave State y y m s expression: D D Q Q D Q = ⋅ + ⋅ C Clk Q Clk Q Y D C y C Q m m = ⋅ + ⋅ Y y C y C s m s William Sandqvist william@kth.se
Exitationstable From the expressions one can directly derive the excitation table (if you can keep it all in your head?) Next state Present Output state CD = 00 01 10 11 = ⋅ + ⋅ Y D C y C y m y Q s Y m Y m m s = ⋅ + ⋅ 00 0 0 0 0 0 0 10 0 Y y C y C s m s 01 00 00 0 1 11 1 10 11 11 00 1 0 0 11 1 1 1 1 01 1 1 1 William Sandqvist william@kth.se
or with help from K-map … Y Y Y m Y m s s C D C D C D 00 01 11 10 00 01 11 10 y m y 00 01 11 10 y m y y m y s s s 00 1 00 00 00 00 10 00 01 1 01 1 1 01 00 00 11 01 11 1 1 1 11 1 1 1 1 11 11 11 11 01 10 1 1 1 10 1 1 10 11 11 10 00 y m C y m C DC y s C = ⋅ + ⋅ = ⋅ + ⋅ Y D C y C Y y C y C m m s m s Change rows and colums to get the binary order as in BV William Sandqvist william@kth.se
Flow table We define four states S1, S2, S3, S4, which gives us the flow table Next state Present Output state Q CD = 00 01 10 11 S1 S 1 S 1 S 1 S3 0 S2 S1 S1 S 2 S4 1 S3 S4 S4 S1 S 3 0 S4 S 4 S 4 S2 S 4 1 William Sandqvist william@kth.se
Flow table Remember : Only one input can be changed at a time • Thus, some transitions will never be able to happen! Next state Present Output state Q CD = 00 01 10 11 S1 S 1 S 1 S 1 S3 0 S2 S1 S1 S 2 S4 1 S3 S4 S4 S1 S 3 0 S4 S 4 S 4 S2 S 4 1 William Sandqvist william@kth.se
Flowtable – impossible transitions Next state Present Output state Q CD = 00 01 10 11 S1 S 1 S 1 S 1 S3 0 S2 S1 S1 S 2 S4 1 S3 S4 S4 S1 S 3 0 S4 S 4 S 4 S2 S 4 1 State S3 Only stable state for S3 is when input is 11 Only one input at a time can change → possible changes are 11 → 01, 11 → 10 • Theese combinations leaves S3! • Input 00 in S3 is not possible! • Input 00 is therefore don’t care ! William Sandqvist william@kth.se
Flowtable – impossible transitions Next state Present Output state Q CD = 00 01 10 11 S1 S 1 S 1 S 1 S3 0 – S2 S1 S 2 S4 1 – S3 S4 S1 S 3 0 S4 S 4 S 4 S2 S 4 1 State S2 Only stable state for S2 is when input is 10 Only one input at a time can change → possible changes are 10 → 11, 10 → 00 • Theese combinations leave S2! • Input 01 in S2 is not possible! • Input 01 is therefore don’t care ! William Sandqvist william@kth.se
D-flip-flop state diagram CD 11 Don’t care is 00 0x ⁄ ⁄ here denoted 01 S1 0 S3 0 11 x0 10 10 by x 0x 0x 11 00 0x ⁄ ⁄ 01 10 S2 1 S4 1 x1 11 10 Don’t care can be used to simplify the circuit (the next state decoder). William Sandqvist william@kth.se
William Sandqvist william@kth.se
Synthesis of asynchronous circuits The synthesis is carried out in the following steps : 1) Create a state diagram acording to the functional description 2) Create a flow table and reduce the number of states if possible 3) Assign codes to the states and create the excitationstable 4) Develop expressions (transfer functions) for next state and outputs 5) Design a circuit that implements the above expressions William Sandqvist william@kth.se
Exemple: serial paritety circuit Input x Output y Odd x y parity y = 1 if the number of pulses at t input x is an odd number. In other words, an "every other time" circuit … 1 0 1 odd odd even William Sandqvist william@kth.se
Create state diagram odd x y parity = = x 1 x 0 = t x 1 A B 0 1 y = = x 0 x 0 B/1 D/0 = = C/1 A/0 A/0 x 1 x 0 x = 1 x D C 1 0 1 0 William Sandqvist william@kth.se
Create state table Odd x y parity t Pres Pres Next State Next State Q Q state state X=0 X=0 1 1 A A A A B B 0 0 B B C C B B 1 1 C C C C D D 1 1 D D A A D D 0 0 William Sandqvist william@kth.se
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