Adapting Asynchronous Circuits to Operating Conditions by Logic - - PowerPoint PPT Presentation

▶
adapting asynchronous circuits
SMART_READER_LITE
LIVE PREVIEW

Adapting Asynchronous Circuits to Operating Conditions by Logic - - PowerPoint PPT Presentation

Nov 25, 2023 109 likes •515 views

Adapting Asynchronous Circuits to Operating Conditions by Logic Parameterisation Andrey Mokhov, Danil Sokolov, Alex Yakovlev Newcastle University, UK Designers dilemma Contradicting requirements: o performance, energy consumption,

slide-1
SLIDE 1

Adapting Asynchronous Circuits to Operating Conditions by Logic Parameterisation

Andrey Mokhov, Danil Sokolov, Alex Yakovlev Newcastle University, UK

slide-2
SLIDE 2
  • Contradicting requirements:
  • ↑ performance, ↓ energy consumption, ↑ robustness
  • high performance → high energy consumption
  • low energy consumption → low robustness
  • high robustness → low performance
  • Competing implementation styles:

– Synchronous – Asynchronous

  • Delay Insensitive (DI)
  • Speed Independent (SI) or Quasi Delay Insensitive (QDI)
  • Bundled data, relative timing assumptions (TA)
  • ...

Designer’s dilemma

slide-3
SLIDE 3

Energy-efficiency v Robustness

slide-4
SLIDE 4

Parameterised Circuits

  • Static parameters set at test/binning stages
  • Dynamic parameters:

– Power management controller – Maintenance mechanisms

slide-5
SLIDE 5

Parameterised Circuits: Trivial Approach

  • Easy to design!
  • Large overheads
  • How can we do better?
slide-6
SLIDE 6
  • Goal:

– Combine circuit implementations efficiently

  • Key observations:

– Externally: the circuits have the same interface – Internally: the circuits behave similarly

  • Solution: use a model that can capture

functional similarities at the circuit level

– Conditional Partial Order Graphs almost fit

Parameterised Circuits: Better Approach

slide-7
SLIDE 7

Conditional Partial Order Graphs

x=0 y=0 x=1 y=0 x=0 y=1 x=1 y=1

slide-8
SLIDE 8

Conditional Partial Order Graphs

 Describe concurrency and causality  Capture similarities in behaviours  Represent families of partial orders

  • acyclic
  • not directly applicable to circuit specification

 Is it possible to specify cyclic behaviour using acyclic objects?

–Yes!

slide-9
SLIDE 9

Describing cycles

slide-10
SLIDE 10

Describing cycles

slide-11
SLIDE 11

Describing cycles

slide-12
SLIDE 12

Describing cycles

slide-13
SLIDE 13

Describing cycles

x = x = 1

slide-14
SLIDE 14

Describing cycles

Initial state: x = 1 set x = 0 set x = 1 x – x +

slide-15
SLIDE 15

Describing cycles

x = 1

 

slide-16
SLIDE 16

Describing cycles

x = 0

   

slide-17
SLIDE 17

Describing cycles

x = 1

    

slide-18
SLIDE 18

Describing circuits: oscillator

x = 0 x = 0

STG Conditional Signal Graphs (CSGs)

slide-19
SLIDE 19

Describing circuits: C-element

STG

slide-20
SLIDE 20

Describing circuits: C-element

CSG

slide-21
SLIDE 21

Describing circuits: C-element

slide-22
SLIDE 22

Describing circuits: C-element

slide-23
SLIDE 23

Describing circuits: C-element

slide-24
SLIDE 24

Describing circuits: C-element

slide-25
SLIDE 25

Describing circuits: C-element

slide-26
SLIDE 26

Describing circuits: C-element

slide-27
SLIDE 27

Describing circuits: C-element

slide-28
SLIDE 28

Describing circuits: C-element

slide-29
SLIDE 29

Circuit composition

C-element AND-gate C/AND-element

slide-30
SLIDE 30

Circuit composition

C-element: ↑ max(a↑, b↑) ↓ max(a↓, b↓) AND-gate: ↑ max(a↑, b↑) ↓ min(a↓, b↓) C/AND-element: can be chosen in run-time!

slide-31
SLIDE 31

Circuit composition

  • Algebraic operations with CSGs:

– Addition (overlay): G1 + G2 – Scalar multiplication (encoding): f  G

  • Composition of C-element and AND-gate:
  • General composition of n circuits:
  • Fast structural operation (if encoding is given)
slide-32
SLIDE 32

Design flow

  • Heterogeneous models

and implementation styles

  • Not computationally

expensive:

– composition is fast – exact encoding is slow but there are fast approximate methods

slide-33
SLIDE 33

Example: Read/Write controller

slide-34
SLIDE 34

Example: possible implementations

Delay Insensitive (DI) T = d + max{d1, d2, d3} + C3 Partial Acknowledgement (PA) T = d + max{d1, d2} + C2 Timing Assumptions (TA) T = d + I Synchronous (CL) T = tclock

slide-35
SLIDE 35

Example: parameterised controller

Can be switched off by power-gating in TA/CL modes

slide-36
SLIDE 36

Example: simulation results

slide-37
SLIDE 37
  • Trivial approach:

– Latency overhead: 120-182%, 122% on average – Energy overhead: 151-330%, 201% on average

  • Our approach:

– Latency overhead: 0-40%, 19% on average – Energy overhead: 0-98%, 23% on average

  • Latency/energy savings at the system level!

Cost of Parameterisation

slide-38
SLIDE 38
  • “Don’t oppose different implementation styles,

take advantage of their benefits!” (reviewer X)

  • New model for circuit-level description and

composition

  • Cost of parameterisation is not prohibitive
  • Future work:

– Tool prototyping – CSC signals awareness – Power-gating mechanisms

Conclusions & Future work

slide-39
SLIDE 39

Questions?