Repetition delay-elements Synchronous sequential circuits clocked - - PowerPoint PPT Presentation

Repetition delay-elements

William Sandqvist william@kth.se

Synchronous sequential circuits clocked flip-flop Asynchronous sequential circuits a trick: Delay Elements Other names: Y and y

Golden rule

William Sandqvist william@kth.se

Exitation table

William Sandqvist william@kth.se

The asynchronous coded state table is called Excitationstable The stable states (those with next state = present state) will be ”encircled”

Present Next state state SR = 00 01 10 11 y Y Y Y Y 0 1 0 1 1 0 1 0

y Y =

Flowtable and Statediagram

William Sandqvist william@kth.se

Present Next state Output state

SR = 00

01 10 11 Q A A A B A B B A B A 1 10 00 11 01 00 10 A 0

⁄

B 1

⁄

11 01 SR

The asynchronous uncoded state table is called Flowtable

William Sandqvist william@kth.se

Hazard ”glitches”

William Sandqvist william@kth.se

• When designing asynchronous circuits it can

happen that you get spikes (glitches) on the signal values

• This is due to the fact that different signaling

pathways have different delay times

• The phenomenon is called hazard and it can

be eliminated by careful design

Quickie Question …

William Sandqvist william@kth.se

What time diagram corresponds best to the signal generated by the following gates at the rising edge?

Alt: A Alt: B Alt: C

in Q

in Q

in Q in Q

1 1 1 1 1 1

William Sandqvist william@kth.se

Alt: A Alt: B Alt: C

in Q

in Q

in Q in Q

1 1 1 1 1 1

Option C does not take into account the delay of the AND gate

x

1

x Because of the delay in the inverters both inputs to the AND gate becomes 1 for a short time

Quickie Question …

What time diagram corresponds best to the signal generated by the following gates at the rising edge?

( A short reset pulse )

in Q

William Sandqvist william@kth.se

The circuit is sometimes used to generate a short reset pulse.

(A short reset pulse )

William Sandqvist william@kth.se

You have seen this before ….

Different types of Hazard

William Sandqvist william@kth.se

Static 1 → 1 Static 0 → 0 Dynamic 1 → 0 Dynamic 0 → 1

Static Hazard

William Sandqvist william@kth.se

Static 1 → 1 Static 0 → 0

Exemple, Static Hazard

William Sandqvist william@kth.se

• Hasard may occur at the following circuit at

the transition of x3x2x1 from 111 ↔ 110

f x

3

x

1

x

2

p q

3 1 2 1

x x x x f + =

Timing diagram

William Sandqvist william@kth.se f x

3

x

1

x

2

p q

3 1 2 1

x x x x f + =

x1 p q f t

x

1

x

2

x

3

00 01 11 10 1 1 1 1 1

1 1 Hazard

Hazardfee circuit

William Sandqvist william@kth.se x

3

x

1

x

2

f

x1 p q f t r p q r 1 1 Hazard-Cover

x

1

x

2

x

3

00 01 11 10 1 1 1 1 1

3 2 3 1 2 1

x x x x x x f + + =

How to avoid static hazard?

William Sandqvist william@kth.se

• The possibility of static hazard is if two adjacent

1's are not covered by a own product term at SOP

• Thus, one can remove the risk of static hazard by

adding groupings so that all adjacent 1's are covered.

• Ex. Hazardfree groupings

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Are these groups enough for freedom of Hazard? cb b d a f + + = f

William Sandqvist william@kth.se

cb b d a f + + = f Hasard cover

• Ex. Hazardfree groupings

Are these groups enough for freedom of Hazard?

William Sandqvist william@kth.se

? ? cb b d a f + + = f The Karnaugh-map is a doughnut!

• Ex. Hazardfree groupings

Are these groups enough for freedom of Hazard?

William Sandqvist william@kth.se

dc cb b d a f + + + = f

• Ex. Hazardfree groupings

Are these groups enough for freedom of Hazard?

William Sandqvist william@kth.se

dc cb b d a f + + + = f Hazard cover

• Ex. Hazardfree groupings

Easy to miss !

• Ex. Hazardfree groupings

William Sandqvist william@kth.se

With another variable order you can not miss! f dc cb b d a f + + + = Hazard cover

Static hazard at POS?

William Sandqvist william@kth.se

• If you have a POS implementation, you have to

ensure that all adjacent 0's are covered by a separate sum term

Dynamic Hazard?

William Sandqvist william@kth.se

• A dynamic hazard causing several glitches

at the output

• A dynamic hazard is caused by the circuit’s

structure

Dynamic 1 → 0 Dynamic 0 → 1

Exemple, Dynamic Hazard

William Sandqvist william@kth.se

• The following equation causes no hazard if

it is implemented as an AND-OR structure

4 1 4 3 2 1

x x x x x x f + + =

Exemple, Dynamic Hazard

William Sandqvist william@kth.se

• But if the equation is

implemented with the following multi-level logic, it will exhibit dynamic hazard

x

2

x

1

x

3

x

4

b a c d f x

2 x 3 x 4

, , x

1

b a c d f One gate delay

How to avoid Dynamic Hazard?

William Sandqvist william@kth.se

• Dynamic hazard can be avoided with two-

level logic

• If a two-level circuit is free from static

hazard, there is also no dynamic hazard!

Quickie Question …

What/which of the following circuits may cause hazard when x changes?

Alt: A Alt: B Alt: C x x x

William Sandqvist william@kth.se

William Sandqvist william@kth.se

Alt: A Alt: B Alt: C x x x Risk for hazard when a=1 and b=0 The extra gate is not covering this case (but a=1 and b=1) a b

Oooops!

not Hazard cover!

Quickie Question …

What/which of the following circuits may cause hazard when x changes?

Quickie Question …

William Sandqvist william@kth.se

Alt: C x Risk for hazard when a=1 and b=0 The extra gate does not cover this case (but a=1 and b=1) a b

Oooops!

not Hazard cover!

ba x 00 01 11 10 1 1 1 1 1 1 ba x 00 01 11 10 1 1 1 1 1 1

b x a

no Hazard

When do one need to take Hazard into account?

William Sandqvist william@kth.se

• In an asynchronous sequential circuit must the

decoder for next state be without hazard!

– Otherwise you could end up in an incorrect state

• For combinatorical circuits hazard is not a

problem because the output always will stabilize after a short time

• In a synchronous sequential circuit hazard is no

problem, as long as you respect setup- and hold- time ( during theese times hazard is allowed to happen! )

Avoid Hazard

William Sandqvist william@kth.se

Static 1 → 1 Static 0 → 0 Dynamic 1 → 0 Dynamic 0 → 1 Static hazard is caused by

• mitted primimplicants

Dynamic hazard can occur when implementing circuits with multi-level logic. Two- level logic circuits which are free of static hazard is also free from dynamic hazard.

Output-spikes in asynchronous circuits

William Sandqvist william@kth.se

Next State Pres state X=0 1 Q y2y1 Y2Y1 00 00 01 01 00 11 1 11 01 10 10 11 10 1

One can get the output spikes in an asynchronous sequential circuits when switching from one stable state to another by passing several unstable states (The phenomenon is no hazard!).

Metastability

William Sandqvist william@kth.se

Input voltage Vx Output voltage

V

f

V

DD

V

x

T

1

T

2

”0” ”1” ”1” ”0” CMOS-circuit transferfunction (eg. inverter)

About metastability

William Sandqvist william@kth.se

D C Q

To understand what metastability is, we can imagine that the input signal D to a latch is very loaded and thus changes very slowly relative to the clock. Suppose further that the clock signal C changes just when D is at VDD/2. Then the latch will be locked at the value that happens to be on D. After some time the latchen will transfer to either ’1’ or ’0’.

1? 0? 1 1

Om metastabilitet …

William Sandqvist william@kth.se

This instability lasts until the transistors in the feedback pleases go to one or the

• ther - but it can take time, and the time will depend on how close VDD/2 that the

locking occurred. We can compare the situation with a ball that lies on top of a hill, or a pencil balanced on its tip. Minimum disruption will get the ball or the pen to fall to one side or the other.

?

If Clk and D switches simultaneously, which value will Q be?

’0’ ’1’

On which side will the ball fall down?

Setup and Hold time (= metastability-protection)

William Sandqvist william@kth.se

• To avoid simultaneously switching, setup and hold

times must be guaranteed :

If Setup and Hold time’s are met, then the flip-flop are guaranteed to behave nicely/deterministic! Setup time is the time D must be stable before Clk changes its value Hold time is the time D must be stable after Clk has changed its value

D Clk

Setup Hold time

Asynchronous inputs?

William Sandqvist william@kth.se

• Unfortunately, we can not always guarantee

that the input is stable through the setup and hold-time

• Suppose you connect a push button on the

D input of a flip-flop

– The user can press the button at any time, even during the setup and hold-time! – The risk is that the flip-flop ends up in a metastable state!

Synchronization of input signals

William Sandqvist william@kth.se

• To synchronize asynchronous inputs you use an extra flip-

flop at the input

• The first flip-flop’s output (A) may end up in a metastable

position

• However, if the clock period is long enough, it will

stabilize before the next clock edge, so that B does not end up in a metastable position!

D Q Q Data Clock (asynchronous) D Q Q Data (synchronous)

A B

(Random numbers with metastability?)

William Sandqvist william@kth.se

Intelprocessors are “tossing a coin" with the following

• circuit. Before the clock pulse becomes ”1” both node A and

node B are logic ”1”. When the clockpulse arrive both inverters will be in their metastable state and pure chance then determines which state inverters finally ends up in.

William Sandqvist william@kth.se

Advanced building elements

William Sandqvist william@kth.se

The asynchronous flip-flops and latches are used as building blocks for secure digital design. New building elements are constantly evolving.

• At the exercise we will construct a double-edge-triggered

flip-flop a new type that may give future computer circuits higher (doubled) performance

• At the lecture, we will now refine the simple SR latch

Example – improved SR-latch

William Sandqvist william@kth.se

• Construction of a set-dominant SR-latch
• Specification

– The construction is a special type of SR-latch (there are no forbidden input 11)

• If S and R are 1 so the latch will be SET (Q = 1)
• The Latch can only go to RESET if

1. both S and R first are S=0 and R=0 (Q = 1) 2. R is then activated (S = 0, R = 1) → Q = 0 !

Source: “Fletcher: Engineering Approach to Digital Design”, Prentice-Hall, 1980. Exemple 10.5 (pp 670).

Recapitulation: SR-latch

William Sandqvist william@kth.se

S R Q

a

1 1 1 1 0/1 1/0 1 (a) Circuit (b) Truth table Q

a

Q

b

R S

Q S SR-Latch R Q S R Q As long as one avoids the input S = R = 1 ( = forbidden combination ) then the outputs Qa and Qb will be each other's inverses. One can then use the symbol to the right.

Q

b

(no change) 1

Forbidden input S=R=1

b a

Q Q ≠

If one takes signals from latches, then there are always inverses available! ?

More problems with the SR-latch

William Sandqvist william@kth.se

S R Q

a

1 1 1 1 0/1 1/0 1 (a) Circuit (b) Truth table Q

a

Q

b

R S Q

b

(no change) 1

If you want to go from SR = 11 to SR = 00, it is a double change

• f input signals. Therefore, we end up either in Q = 0 or in Q =

1 no one can know!

• This is another reason to exclude SR = 11.

SR-latch

William Sandqvist william@kth.se

a d

00 10

SR

10 00 01 11

Q=1 Q=0

01 11

SET-dominant SR-latch

William Sandqvist william@kth.se

e f b c a d

00(10)

) ( Q Q SR

00(10) 01(10) 10(10) 10(10) 00(10) 01(01) 01(01) 11(10) 11(10) 10(10) 11(10) 00(01) 01(01) 00(01) 01(10) 11(10)

11 = SR

Q=1 Q=0

Desired behavior

William Sandqvist william@kth.se

Usual SR-latch Set-dominant SR-latch SR=11

SET-dominant SR-latch

William Sandqvist william@kth.se

e f b c a d

00(10)

) ( Q Q SR

00(10) 01(10) 10(10) 10(10) 00(10) 01(01) 01(01) 11(10) 11(10) 10(10) 11(10) 00(01) 01(01) 00(01) 01(10) 11(10)

1 1 1 1 1 1 10 11 01 00 − − − − − − e f a f b e f e e d c d b d c c b e a b b d a a Q Q ) ( Q Q SR 11 = SR

State e ”takes care of” the case SR = 11

Compatibility

William Sandqvist william@kth.se

a (10) b (10) e (10) f (10) c (01) d (01)

There are no equivalent states, are there any Moore-compatible states … ?

Kompatibilitet

William Sandqvist william@kth.se

a (10) b (10) e (10) f (10) c (01) d (01)

a(10): ad-b b(10): a-eb b(10): a-eb e(10): -feb b(10): a-eb f(10): afe- e(10): -feb f(10): afe- c(01): cd-b d(01): cde- Many choices ...

Compatibility graph

William Sandqvist william@kth.se

a (10) b (10) e (10) f (10) c (01) d (01)

− − − − − − − 1 1 1 10 11 01 00 a e e a e a e c c c a e c a a Q Q

New names a (ab), e (ef), c (cd) Three states needs two state variables Y2 och Y1 Reduced flowtable

) ( Q Q SR

Many choices ...

State encoding

William Sandqvist william@kth.se

a e c

1 2y

y

the chosen state encoding (Gray) ?

From c to e requires a "double change" of Y2Y1 this is modified by the transition state to two changes after another.

2

1 , y Q Q c Q e a = = =

Transition-state

Output code

: a : e : c

Karnaugh maps

William Sandqvist william@kth.se

1 2 1 2 2

y Ry y R S y S Y + + = SR Ry Y + =

1 1

Hazardfree circuits directly!

Circuit-schematic

William Sandqvist william@kth.se 1

y Here we have our ” foolproof” SR-latch!

1 2 1 2 2

y Ry y R S y S Y + + = SR Ry Y + =

1 1

Q y Q y = =

2 2

Bad luck!

William Sandqvist william@kth.se

• What will happen if we write 11 (instead of 01) as a unstable state in the

square number 3, on pure speculation that this will give us a simpler circuit? From 00 in square 2 to 11 in square 3 there is a safe dubblechange. Will it be 01, you end up in stable 01, will it be 10 you go to 11 and finally to stable 01.

An other solution?

In addition to solving the problem of double change, as we have already have done, we want to get as simple as possible network!

New Karnaugh maps

William Sandqvist william@kth.se

• From 00 to 11 it is a

harmless double change of state variables that in the end always leads to stable 01.

1 2 2

y R y S Y + = SR Ry Y + =

1 1

Easier circuit! We introduced a non- critical Hazard and it gave us greater groupings and a simpler network!

Foolproof and compact

William Sandqvist william@kth.se

Q y Q y = =

2 2 1

y

2

y

1 2 2

y R y S Y + = SR Ry Y + =

1 1

Asynchronous circuits are the building blocks

William Sandqvist william@kth.se

Because the asynchronous sequence networks are used as building blocks for all other Digital Design, it is common to make great efforts to get them as optimal as possible. They are used more often in the thousands in a design than individually. Each input gate "costs" and counts!

Are dominant SR-latches used?

William Sandqvist william@kth.se

PIC16F690 IO-unit, SR-latch

The latch is RESET-dominant SR 11 → 1 = = Q Q

William Sandqvist william@kth.se

PIC16F690 IO-enhet, SR-latch

William Sandqvist william@kth.se

Touch control. The usage of the SR-latch is a capacitively controlled oscillator. It changes the frequency at a "touch"

• f your finger.

f f f ∆ − =

William Sandqvist william@kth.se