Outline Introduction Delay Test Issues Our Solutions Improved - - PDF document

DESIGN FOR AT-SPEED DELAY TEST

Youhua Shi

Information Technology Research Organization Waseda University

Outline

• Introduction
• Delay Test Issues
• Our Solutions

– Improved Launch Delay Testing – Power-aware Test Technique

• Conclusions

Introduction

What is Driving Modern Test Technology?

• SoC Design

– Massive Integration – Time-to-Market

• Deep-Submicron/Nanometer Design

– New Failure Modes – Massive Integration

DSM/Nanometer Design

• In DSM design problem focus moved

– (.5u) Delay moved into route – (.35) Clock skew and routing congestion – (.25) Power delivery

Stuck-at Test IDDQ Test

Functional Test

Complete Test Strategy

Delay Test

• In Nanometer design

– (180) Faults predominantly in route – (130) Background leakage in tens of mA – (<90) ???

Why Do At-Speed Delay Testing?

• Timing-Related Defects

– a 20X increase in timing-related defects moving from 180nm to 130nm – 20 – 50% of the test escapes are timing related

• To detect the timing related

defect 2 conditions are required:

– The pattern should generate a transition – The transition propagation should be captured at-speed

Source: NVIDIA 2003

Complex Failure Modes Require New Design for Test techniques.

At-Speed Delay Test

• At-speed delay testing is a MUST!!

– improve manufacturing quality – maintain DPM rates in nanometer designs

• Delay fault models

– Transition fault model For testing gross delay defects at a node

• Tests combined delay through all gates of a path
• Requires paths as input

– Path delay fault model For testing distributed delays along a path

• Tests for a gross delay potential at each gate

terminal

• Paths are automatically selected to test transition

faults

Stuck-at Test IDDQ Test Functional Test Complete Test Strategy Delay Test

Fault site Faulty path

Transition Delay Test

Launch-on-shift Launch-on-capture

Shift Shift Last Shift Shift SE CK Capture Launch Shift Shift Dead Cycles Shift SE CK Capture Launch

LOS vs. LOC

Launch-on-shift

• Advantages

– Combinational ATPG

• Higher coverage, fewer

pattern, faster runtime

• Disadvantages

– Must disable scan enable quickly

• Scan enable must be routed

as a timing critical clock

– Can create non-functional patterns

• Possible to cause overtest

Launch-on-capture

• Advantages

– Fewer requirements on the scan control logic and is easier

• Shifting can be done at any

speed

• Scan enable doesn’t have to

be routed as a critical clock

• r pipelined
• Disadvantages

– Sequential ATPG (at least 2 system clock cycles)

• Medium coverage, more

patterns and longer runtime

Most customers use LOC delay test!

At-speed Delay Test Issues

Delay Test Strategy

Quality Cost Power

Test pattern, test time, ATE, etc

Fault coverage etc. Power, IR-drop, frequency, etc Small delay,

• vertest, etc

Issue I. Cost vs. Quality

quality

cost

• Transition pattern data

volume 4x-6x more than stuck-at

• Method to reduce test

cost

– Test Compression

• What can be done in the

design?

– Design for delay test

Solution: Improved Launch Delay Testing

• Objective

– Higher fault coverage – Less patterns

• Basic Idea

– Two launch mode

• LOS mode

– Launch-on-shift using slow scan enable

• Mixed launch mode

– LOC + LOS

Shift Shift Last Shift Shift SE CK Capture Launch Shift Shift Dead Cycles Shift SE CK Capture Launch

Solution: Improved Launch Delay Testing

q(so) mode sel se d si clk

lse

Experimental Results Concluding Remarks

• DFT technique for better test quality and

lower cost

• Left work

– ATPG development – Optimized SFF selection

• Use Launch-on-Shift for majority of coverage
• Use Launch-on-Capture for higher speed clock domains

and critical path

Issue II. Power in Delay test

• Power has become the main challenge for

nanometer designs

• Power consumption during test mode is higher

– 3-8X as compared to functional mode – 30X in low power devices!!!

• Such high difference in power consumption

can lead to permanent damage

• Reliability failures due to higher junction temperature and

increased peak power

• May result over kill by power consumption in test mode

Methodology needed to be address this issue

Issue II. Power in Delay test

Solution: Test Power Reduction

• Test Power

– Scan shift power – Capture power

• Our solutions

– Intelligent X-filling in test data compression (done)

• Power reduction is around 40%

– DFT for shift power reduction (done)

• Prevent switching in the comb. logic during shift
• Shift power is reduced up to 10X
• However, Peak power is increased

– DFT for power reduction in delay test (ongoing)

Solution: Test Power Reduction

• DFT for power reduction in delay test

– Capture power aware ATPG – Intelligent X-filling – Transition Loading Scheme

Conclusions

• Nanometer designs require delay test to

maintain high test quality

• Delay test increases test cost
• DFT techniques could reduce test cost while

maintaining high test quality

• Future work

– Small delay test – Avoid over kill in delay test – DFT techniques for emerging processor architecture, power-gating circuits, etc

Thank You!!!

• Questions ?
• Comments / feedback welcome:

<shi@yanagi.comm.waseda.ac.jp>