[PPT] - Interconnect Gate delay Wire delay The delay in VLSI circuits PowerPoint Presentation

SLIDE 1

1 Advanced Digital IC-Design

Interconnect

Propagation Delay

Lumped C

Gate delay Wire delay

p model Distributed C model The delay in VLSI circuits have two components

Gate delay (t pHL/ t pLH) Wire (interconnect) delay (t w)

The Wire & Decreasing Feature Sizes

Change in deep submicron A i l l d i Active elements are less dominant Wiring analysis is thus essential for Speed Power Reliability

Interconnect

0.08 Connection Probability

Global Wires do not scale with the technology Local Wires Global Wires

0.06 0.04 0.02 1.0 0.2 0.8 0.6 0.4 Wire Length/Chip Diagonal Length

SLIDE 2

2 Mid 80: ties

Mostly gate delay

Wire Delay Dominates Today

85% 15%

Mid 90: ties

Gate delay and wire delay

50% 50%

Today

Mostly wire delay

20% 80%

Wire Parasitics

Wire

Parasitic classes Capacitive

Substrate Wire

Resistive Inductive Reduces Performance Reduces Performance Increase Power Consumption Affect Reliability

Reliability Problems

Power supply noise Cross talk - capacitive and inductive coupling Transmission line effect (ringing effect)

These effects will degrade the reliability in the digital system Power Supply Noise

V

VDD RWire ISwitch

VDD

V RWire

Resistive & inductive parasitics

SLIDE 3

3 Power Supply Noise

Logic failure probability is accentuated when li d th l lt scaling down the supply voltage

Improvements

Reduce wire resistance (copper, wider wires) Reduce pin inductance (good packages) Stabilize power supply (on chip decoupling) Stabilize power supply (on-chip decoupling)

Cross Talk

CC

li

V V

A voltage or a current change may influence

CCoupling V I Mutual Inductance

g y the signal on a parallel wire, especially on:

Long wires Sub micron technology Several metal layers

Inductance I

y

Capacitive and inductive coupling Long Wires are Sensitive

V V V V/ 2

Ideal

V V/ 2 V V/ 2 Degraded

Ringing effect due to i d inductance Possible logic error

Where

Large silicon designs

In global interconnects (System-on-Chip)

Especially in Mixed-Signal Design

coupling of digital and analog signals

SLIDE 4

4 Transmission Line Effect

Consider a 3 GHz Pentium The wavelength is calculated by The wavelength is calculated by

8 8 9

3 10 m/s 3 GHz 3 10 0.1m 3 10 c f c f λ = × = × = = = ×

l ff

We have to be aware of the transmission line effects!

Transmission line effects are important at

0.1m 1 cm 10 10

wire

L λ ≈ = =

Transmission Line Effect Improvements Proper Impedance matching Avoid unnecessary long signal routing Design the transmission line as close to ground as possible Buffering Buffering Cross Talk Reduction Techniques

Widen the spacing between signal lines Route signals on different layers;

rthogonal to each other

Minimize parallel run lengths between signals

Cross-Talk Example

2 2 2

3 1 m 3 m 0.057 fF/ m 0.171fF 2 3 0 0 4 f / 0 324 f

plate

Overlap C C μ μ μ = × ≈ × =

Overlapping wire

VDD

A 2.5V transition give

2 3 m 0.054 fF/ m 0.324 fF 0.5 fF 6 fF

fringing x L

C C C μ μ ≈ × × = = =

Out PDN In

φ CL CX φ

DD

6 2.5 2.3 6 0.5

L

ut

DD L X

C V V V C C = = = + +

Capacitive voltage division

SLIDE 5

5 Cross Talk on a Bus

Bus The cross coupling C have double swing Bus Miller effect increase the cross talk

Reducing Cross-Talk

GND

Shielding Wire

Avoid parallel wires Shielding

VDD

Shielding Layer

GND Substrate GND

Swizzled Bus Routing

Switch the bit order every turn Reduces the coupling educes t e coup g Reduces noise

7 5 3 1 6 4 2 7 5 3 1 6 4 2 7 5 3 1 6 4 2 7 5 3 1 6 4 2 Source: Intel

Interleaved Busses

Busses with different switching time Reduces the coupling Reduces noise

Source: Intel

SLIDE 6

6 Metal Layers A 3D Problem! Capacitance: Parallel Plate

SiO

Metal/Poly etc.

SiO2 t L H W

x
x

WL C t ε =

Substrate

tox

15

x

ε 3.5 10 / F cm

−

= ×

2

for SiO

Capacitance: Fringing

H W H W H W

Metal Layers Metal Contacts (via)

Note

Fringing C

the Size!

SLIDE 7

7

6 Capacitance pF/cm

Impact of Fringing Capacitance

Fringing capacitance

1

Cplate H/tox=1 H/tox=0.5

dominates for small W/ t ox

0.35μ ≈ W=H=tox

W

0.1 0.1 10 1 0.4

W/tox

4

H tox H

Wire Resistance

Sheet Resistance

R

L L R R ρ = × = ×

L

R R R R R

R R

W H W

Metal/Poly etc.

H W

R R

R R R R

Silicide

Silicide to reduce the poly resistance

Polysilicon Silicide SiO2

n+ p- n+

Advanced technologies have silicide on poly

Using Bypasses (e.g. in memories)

Driving a word line from both sides Using a metal bypass

Driver Polysilicon word line Metal word line

Using a metal bypass

Polysilicon word line Metal bypass

SLIDE 8

8 Repeaters Reduce Delay

RC increases quadratically with the length

Driver Wire With repeaters

The Elmore Delay

1 1 1 2 2 1 2 3 3 1 2 3 4 4

τ R C (R R )C (R R R )C (R R R R )C = + + + + + + + + +

C1

R6 R5 R4 R3 R2 R1 C4 C5 C6 C3 C2 Idea: The resistance from source to node 3 is R1+ R2+ R3. That resistance should thus be used to load C3

Distributed RC-Line

Lumped

R R

Distributed Lumped Model Distributed

r Δ L C C c Δ L r Δ L r Δ L c Δ L c Δ L

Distributed RC-line Model

L

c Δ L c Δ L c Δ L

RC-Models

Lum ped Distributed t p (0 -> 50% ) 0.69RC 0.38RC RC (0 -> 63% ) RC 0.5RC t r (10% -> 90% ) 2.2RC 0.9RC

Lumped model tends to be pessimistic

SLIDE 9

9 Lumped Model (Elmore Delay)

1300 ; 1000 0.2 ; 1.1 ; 0.8

eq p wire int wire L

R R C pF C pF C pf

− =

Ω = Ω = = =

1 12 12 2

0.69 (1300 1000) 1. 0.6 1 10 0.69 1300 0.2 1 9 (1300 1000) 0 3.1 . 9 8 1

pHL

t ns

− − −

= + + + = = + × + × × × × × + × × × 0.69 ( ) 0. 0. 6 6 ) 9 9 (

eq p wire wire eq p w eq p i ire L p L nt H

R R C R R t C R C

− − −

= × × + + + × + + × + ×

Cint CL Req-n Req-p

10 m m long wire

Distributed Model (Elmore Delay)

3.19 ns when the lumped model was used 1300 ; 1000 0.2 ; 1.1 ; 0.8

eq p wire int wire L

R R C pF C pF C pf

− =

Ω = Ω = = =

2 12 12 1

(0.69 1300 0.38 1000) 1.1 1 0.69 1300 0.2 10 .69 (1300 1000) 0.8 2. 1 5 8

pHL

t ns

− − −

= + + + = = × + × × + × + × × × × × × (0.69 0.38 ) 0.69 .69 ( )

eq p wire wire eq p in eq p w t i L pH re L

R C R C t R R R C

− − −

× × = + + + × × × + × + +

Cint CL Req-n Req-p

10 m m long wire

Driving a Large Fan-Out

Typical examples: Busses

Driving a large capacitance

Clock network Control wires (e.g. set and reset signals) Memories (driving a large number of storage cells)

VDD

Worst case: Off chip signals

CL

Driving Large Capacitances

Cint = Intrinsic capacitance Cext = Extrinsic capacitance Req Req = Resistance in channel

VDD

Cint = Cdb+Cgd Req

ext w g

C C C = +

Cw = Wire capacitance Cg = Gate C in next stage

Cint

DD

Cext Req Req

SLIDE 10

10 Scaling to increase driving capability

Scaling W with a factor S:

Req Cint = Cdb+Cgd Req

int iref ref eq

C S C R R S = × =

VDD

Cint

DD

Cext Req Req

Scaling to Increase Driving Capability

Delay RC-model

0.69 ( ) 0.69 (1 )

ext p eq int ext eq int

C t R C C R C = + = + 0.69 ( ) 0.69 (1 ) 0.69 (1 ) (1 )

p eq int ext eq int int ref ext ext p iref p iref iref

t R C C R C C R C C t S S C t C S S C + + = + = +

Scaling with a factor S tp0 = intrinsic delay Independent of S

Scaling Example

19.3 ; 3.15 ; 3.0 1 (1 ) 19 3 (1 )

p ext iref ext

t ps C fF C fF C t t = = = + +

0 (1

) 19.3 (1 ) 1.05

ext p p iref

t t S ps C S = + = + ×

C C Ciref Cext

Scaling Example (p206)

1 19.3 (1 ) 1.05

p

t ps S = × + ×

30 40

tp (ps)

S = 5, Substantial improvement S > 10, ”No more gain”

S

5 10 15 10 20

SLIDE 11

11 Sizing a Chain of Inverters

Each stage is scaled with

2 N 1

Each stage is scaled with the same factor f

Cg,N+1= CL Cg,1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Scale factor optimum is

Sizing a Chain of Inverters

2 N 1

(1 ) f

e f

γ +

=

Cg,N+1= CL 2 N Cg,1 1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

Sizing a Chain of Inverters

(1 ) f

e f

γ +

=

Has no closed form solution except for γ= 0

f

so u o p

γ

γ= 0 when intrinsic capacitance is neglected

f e =

Otherwise: f is solved numerically

Cg,N+1= CL 2 N Cg,1 1 Cint,1 Cg,2 Cint,2 Cg,N Cint,N

6 Too many stages

p popt

t t Normalized delay

Sizing a Chain of Inverters

6 4 Common Practice Around 4

f

2 1 2 5 4 3

1 (1 ) f

e f

+

= for

SLIDE 12

12 Tri-state Buffers

VDD

En En Out

VDD

En En In In Out

Multiple Power Supply Voltages

Divide a design into regions The regions can be locally clocked Reduces the wiring problem Reduces the wiring problem Decrease the supply voltage on each module as much as possible

1 3

Power can be saved

5 2 4

Two or three voltages is often a optimum solution Not much difference in power between two and three voltages Overhead: DC-DC converters, control logic

Multiple Power Supply Voltage

Overhead: DC DC converters, control logic …

0.6 0.7 0.8 0.9 1

wer consumption

With overhead

1 2 3 4 5 6 7 8 0.4 0.5 Number of supply voltages

Relative po

Without overhead

Vhigh

Signal level converter

Needed when going from low to high voltage blocks

I n Out g Vlow I n Out Vhigh Vlow

SLIDE 13

13 Chip Layout

Automatic supply voltage assignment Blocks choose high or low voltage Large PMOS transistors are used as switches g

locally clocked modules

VDDhigh VDDlow

Large P- channel transistors Supply voltage management unit

Power and Ground Distribution

Leaf Cells Leaf Cells

VDD

Leaf Cells Leaf Cells Leaf Cells Leaf Cells

Lower level (Metal 1-2)

Leaf Cells Leaf Cells

GND

A Three Metal Layer Approach

Every second line for VDD and GND 90% of 3rd metal layer used for power ( l k) ti (clock) routing

Metal 3 Metal 2 Metal 1

Source: Compaq

A Four Metal Layer Approach

Grid for VDD and GND 90% of 3rd and 4th metals used for power (clock) routing power (clock) routing

Metal 3 Metal 4 Metal 2 Metal 1

Source: Compaq

SLIDE 14

14 Solid planes dedicated to VDD and GND Significantly lower resistance

A 6 Metal Layer Approach

Lower inductance

Metal 4 VDD Metal 3 Metal 2 Metal 1 GND

Source: Compaq

Standard Cell Routing - Manhattan

y destination

Cell-structure hidden under

y x Manhattan source

hidden under interconnect layers

Diagonal Wiring

destination

diagonal

y x Manhattan source

20% interconnect length reduction 20% interconnect length reduction Increased clock speed 15% Smaller chips 30% Via reduction

Source: Cadence

Place & Route (2-3 Metal Layers)

Placement of library cells Filler cell Routing

Tools:

Placer
Router

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell

g channel Routing

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell

SLIDE 15

15

Leaf Leaf Leaf Leaf Leaf Leaf Leaf

Place & Route (3-10 Metal Layers)

No Routing channels needed

VDD Placement of library cells Routing

Leaf Leaf Leaf Leaf Leaf Leaf Leaf Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Cell Cell Cell Cell Cell Cell Cell

GND VDD

Upside-down Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Cell Cell Cell Cell Cell Cell Cell

GND VDD

Upside-down

Filler Cell

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell

Standard Cells and Macro Cells

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell

Macro Cell

Macro cells are used for regular structures like RAM: s and sometimes lti li

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell

e.g. Memory

multipliers

Block (power) rings are often used on large blocks

Power and Block Rings (5 Metal Layers)

Separate supply for the pads

RAM

Power rings around the core Bl k i d

Synthesized Block RAM

Block rings around the two blocks (MP3 Accelerator – IC project course)

SoC – A Question of Reuse

Reused Architecture Custom block in

Radio

Embedded RAM

L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C Leaf Cell L e a f C L e a f C L e a f C Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C Leaf Cell L e a f C L e a f C L e a f C Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell

Acelerator Macro Cell block in Standard Cell Analog IP-Block Analog

Radio Baseband RAM PLL DA

L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell e ll e ll e ll e ll L e a f C e ll Leaf Cell L e a f C e ll L e a f C e ll L e a f C e ll Leaf Cell Leaf Cell e ll e ll e ll e ll

ARM

Processor

RAM

Macro Cell IP Block IP-Block Digital IP-Block IP = Intellectual Property i.e. a block that designed and put on to the market

DA

SLIDE 16

16 Low-k Dielectrics to Reduce Capacitance

x

plate

x

WL C t ε =

New Low-k materials reduce the C Low-k materials are porous and much less dense than silicon dioxide (Compare with High-k that is used in the thin oxide to increase the C) ITRS roadmap

ε

Tech- nology 0.25 μm 0.18 μm 0.13μ m 0.1 μm 0.07 μm 0.05 μm Dielectric constant 3.3 2.7 2.3 2.0 1.8 1.5

Copper Wires

Used in sub-0.25 μm technologies (e.g. IBM and Motorola) and Motorola) 2.2 μΩ/ cm for Cu and 3.5 for Al give a 40% reduction in resistance 100X longer life time, due to lower electro migration

Vias

Advanced Digital IC-Design

Interconnect Cont.

Student Lectures

Send your slides to me, latest the night before your presentation Preferred format - .ppt or .pptx You will be evaluated by your fiends Please look at the template: Please look at the template:

http: / / www.eit.lth.se/ course/ eti135 -> Presentations

SLIDE 17

17 Home Exercises

Solutions to 4 hand-in Solutions to 4 hand in assignments are required, se

http: / / www.eit.lth.se/ course/ eti135 -> Home Exercises

Deadline: March 8 Invited Lectures

Advanced Digital IC Design

Static tim ing analysis Design For Test g

Both from ST-Ericsson

Layout Die Photo

Bonding Pads for Off-Chip Connections Pad Frame Package Bonding wire (inductive) Chip

SLIDE 18

18 Bonding Pads for Off-Chip Connections

Bonding Pad GND Out 100 μm Output driver VDD GND Out

Driving a Large Capacitive Load

Layout styles for wide transistors

Several contacts give low R Finger Folded Circular

Input Pad: ESD Protected

VDD Gates are sensitive to Limits static currents PAD R D1 D2 X C static voltages Sinks static voltages Diode

Output Pad

Folded Transistor Pad Surface Bond Wire

SLIDE 19

19 Pads in 0.8 um Technology

Output Pad Wide wires and many contacts to reduce R Buffer, Folded P Folded Tran- sistor Power Pad

Decoupling Capacitors

Board wiring Bonding wire C 1 SUPPLY Decoupling capacitor CHIP Cd 2

About 10X the switched capacitance

Decoupling capacitors are added: On the board (close to the supply pins) On the chip

MOS-transistor Decoupling C, 0.8 um

VDD

Leaf Cell Routing Routing Channel

Filler Cells in a Typical 0.13 um Tech.

Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell Leaf Cell

VDD

Leaf Cell

VDD

Decoupling C capacitance when there is space left

SLIDE 20

20 Electro Migration

1mA/um I

max DC,

≈