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１． Background ２． 3D LSI
- Current 3D LSI technology
３． Heterogeneous Multichip 3D LSI: COOL System ４． COOL Interconnect
- Protocol
- Interface Circuit Design
COOL Interconnect COOL Interconnect Low Power Interconnection - - PowerPoint PPT Presentation
COOL Interconnect COOL Interconnect Low Power Interconnection - - PowerPoint PPT Presentation
COOL Interconnect COOL Interconnect Low Power Interconnection Technology Low Power Interconnection Technology for Scalable 3D LSI Design for Scalable 3D LSI Design Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi
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Background Background
IT機器における国内総電力消費量と CO2排出量予測（2006～2050)
A breakthrough in the reduction of LSI energy consumption is needed The key is not in the miniaturization, is in the efficient use of its transistors
Reasons f Reasons for
- r the
the increase increase of
- f
energy consumptio energy consumption ・Very high number of units ・Increase in features ・Amount Amount of
- f data an
data and d Communi mmunication s cation spee eeds ds
Utilization Wall
・the number of active transistors within any given semiconductor chip has exponentially decreased accordingly with its miniaturization ＜Multicore miniaturization＞
Leakage current increase due to semiconductor miniaturization
Consumption in IT devices ・Appliances (IT) ・Network switches ・Data Center
Low power technology ・Clock gating ・Dual Vt ・Static back-gate bias ・Dynamic back-gate bias ・Power cut-off ・DVFS technology ・Low voltage
Consumption requirement in mobile devices
(800mW-1000mW)
Always increasing power consumption
Classical scaling Leakage- limited Scaling Transistors S2 S2 Frequency S S Consumption (Cap) 1/S 1/S Consumption （Vdd） 1/S2 ～1 Utilization 1 1/S2
4 Cores@2GHz 65nm 8 Cores@2GHz 32nm 4 Cores@4GHz 32nm
・Can’t increase freq ・Only 8 cores are used
・ ・
【Challenges】 ・Energy consumption limit ・Increase in leakage current ・Operation frequency limit Dark Silicon
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Different technologies like common circuit logic, memory, etc. can be freely stacked to surpass Moore’s Law
More than simple integration, the processor architecture also change to mitigate the Utilization Wall, the Memory Wall, the Power Wall and the ILP Wall
【Advantages of a scalable 3D LSI】
－Low power consumption －High level integration －High performance －Short-to-market cycle －Flexibility －Low cost
Scalable 3D LSI
Through-silicon via （TSV）
Ideal
Stacked LSI based on application requirements I/O Memory Processor 129 chips stacked in a 3D LSI ISSCC2010 Keio U/ Prof. Kuroda 8Gb 3D DRAM ISSCC2009 Samsung 4 layer stacked memory cell ISSCC2010 Unity Semiconductor
Standardization of inter- chip communication ・Easy to design ・Easy to dest
Current state
3D LSI 3D LSI
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Through-silicon via（TSV）
3D integration technology that uses microbump bonding and adhesive injection Main stacking methods:
- Wafer on Wafer
- Wafer on Chip
- Chip on Chip
Memory Ｉ/Ｏ Processor
Current 3D LSI Technology Current 3D LSI Technology
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Low power heterogeneous Multichip/Multicore Microprocessor architecture designed for 3D stack chips Distributed software technology that effectively drives the hardware Scalable interface technology for low power 3D LSI chips
Interface logic Memory
Distributed processing Heterogeneous Multichip/Multicore
Shared bus
Peripheral Chip
Heterogeneous Multichip 3D LSI: Heterogeneous Multichip 3D LSI: COOL System COOL System
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COOL Interconnect COOL Interconnect
Physical layer Physical layer Circuit layer Circuit layer
Multilayer IP
Logic layer Logic layer
Fabrication Process of 1600 TSV in 40x40 array
D Q Q D Q D
Interface driver Scalable bus interface logic
COOL Interconnect Interface Chip ID Bus arbiter Data converter I/O (C) I/O (B) I/O (A)
ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology
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Interface logic Shared bus (1600 TSV)
COOL Interconnect COOL Interconnect
ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology
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Interconnection type：Shared bus Communication model：Multi-Master / Multi-Slave （No of Master chips：Max 16, Slaves：Max 16） Protocol：3-stage pipeline －S0 : Request phase －S1 : Address / command transmission phase －S2 : Data transfer phase ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology
Protocol (1/2) Protocol (1/2)
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Data transfer throughput ：1 cycle Data transfer latency ：2 cycles Arbitration model： Dual distributed －Bus-Master －Bus-Slave Transfer mode：single, burst、lock
Through TSV’s these signals reach all chips within the 3D LSI stack and communicate using an implemented common interface logic
COOL Interconnect‘s data signals consist of 1024 out of 1600 TSV COOL Interconnect‘s data signals consist of 1024 out of 1600 TSV
ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology
Signal type Description bus_clock
- Bus clock
bus_reset
- Bus reset
bus_req_m(15:0) S0 Request Master bus_req_s(15:0) S0 Request Slave bus_s_stat(15:0) S0 Slave Status bus_command(3:0) S1 Command bus_address(31:0) S1 Address bus_destination(3:0) S1 Destination bus_lock S1 Bus lock bus_data(1023:0) S2 Data bus_data_valid(6:0) S2 Data Valid bus_ready S2 Data Ready bus_error S2 Data Error
Protocol (2/2) Protocol (2/2)
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0.562 0.526 0.512 0.494 0.493 0.498 0.504 0.385 0.414 0.427 0.434 0.449 0.460 0.470 0.480 0.664 2.97 1.59 1.46 0.73 0.48 0.36 0.28 5.90
0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 X1 X2 X3 X4 X8 X12 X16 X20
Driver Size Power Consumption [W@50MHz/1600pins]
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
Noise [VnS]
Noise Receiver cirucit consumption Driver and reciver circuit consumption D Q Q D Q D
x12 Interface driver
Cool Interconnect DDR‐2(1) Circ. 0.67 mm2 8.64mm2 Area I/O 4 mm2 4 mm2 Consumpt 246.5 mW (max)(2) 576 mW Bandwidth 6.4 GB/s 6.4 GB/s Freq 50 MHz 400 MHz
Driver circuit optimization through simulation Driver circuit optimization through simulation
(1) DDR-2 PC-6400 (2) Estimation
Comparison with current interconnection technology
ＣＯＯＬ Ｉｎｔｅｒｃｏｎｎｅｃｔ Technology
Interface Circuit Design Interface Circuit Design
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・ Bandwidth： 6.4GByte/sec ＠50MHz ・ Inter-chip connection： 1600 TSV ・ Model：Multi-Master / Multi-Slave Shared bus
Master（CPU）： Up to 16 chips Slave（Memory/IO）： Up to 16 Chips
Technology TSMC0.25um ・Interface are：4.67mm2
Interface circuit： 0.67mm2 (14%) TSV area： 4mm2 (86%) Logic TEG I/O pad TEG TEG TEG 8.3ｍｍ 6ｍｍ TSV array
2.16ｍｍ 2.16ｍｍ
Scalable 3D LSI chips interface verification and test
(a) Conventional I/O area (4mm2) (b) TSV area (4mm2) 5ｍｍ 5ｍｍ 0.2ｍｍ 5ｍｍ 5ｍｍ
2ｍｍ
Same area
Test Chip Test Chip
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- Scalability of 3D LSI designs will play a crucial role in
extending the silicon road-map for the next generation of microprocessor IPs
- We presented a working model of a standard
interconnection bus for 3D LSI units that provides scalability as well as high performance and low power consumption
- Implementing a standard way of inter-chip communication
common challenges can be avoided or completely solved.
- COOL Interconnect provides the necessary versatility to
design 3D LSI efficiently made for the application with a short-to-market cycle and easy fabrication process
Summary Summary
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- Increased power densities that can result from
carelessly placing one computational block over another
- Find ways to collaborate with open innovation
business partners to create a new standard
Future Work Future Work
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COOL Chips XIV COOL Chips XIV This research is supported by the New Energy and Industrial Technology Development Organization (NEDO)