At-Speed BIST for Board-Level Interconnect Artur Jutman - PowerPoint PPT Presentation

EBTW05 EBTW05 At-Speed BIST for Board-Level Interconnect Artur Jutman artur@pld.ttu.ee Tallinn University of Technology, ESTONIA EBTW 2005, Tallinn, Estonia Slide 1

Outline EBTW05 EBTW05 1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Summary and Discussion EBTW 2005, Tallinn, Estonia Slide 2

Outline EBTW05 EBTW05 1. Introduction • PCB testing challenges • Characteristics and desired properties of interconnect self-test framework 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Discussion EBTW 2005, Tallinn, Estonia Slide 3

PCB Testing Challenge EBTW05 EBTW05 Challenges Challenges • • PCBs are getting complex PCBs are getting complex • • Up to several k nets on PCB Up to several k nets on PCB • • New faults getting involved New faults getting involved • • Test access is getting limited Test access is getting limited • • Workforce factors Workforce factors How to cope? How to cope? • • ICT, X- -ray, optical? ray, optical? ICT, X • • Functional testing or BIST? Functional testing or BIST? EBTW 2005, Tallinn, Estonia Slide 4

Limitations of Traditional Methods EBTW05 EBTW05 Usage of traditional interconnect testing methods at different Usage of traditional interconnect testing methods at different levels of technology: levels of technology: In-Circuit Test Boundary Scan X-Ray & Optical Inspection Board level Small boards, static BS-compliant Limited interconnect boards, multi-board fault coverage interconnect faults only systems, static faults only Network-on- Not applicable Applicable as a Not applicable at this moment Chip concept only Conclusions: Conclusions: • • dynamic fault testing is not possible with traditional methods dynamic fault testing is not possible with traditional methods • • interconnect testing solutions for NoC are missing interconnect testing solutions for NoC are missing EBTW 2005, Tallinn, Estonia Slide 5

Introduction EBTW05 EBTW05 • Characteristics of an interconnect self-test framework: • Test pattern generation (TPG) Fault models (static vs. dynamic faults) and fault coverage – Deterministic, pseudo-random, and weighted sequences – TPG hardware – • Test application Test access mechanism (BS, in-circuit test, custom solutions, etc.) – Test-per-scan vs. test-per-clock – At-speed testing vs. low-speed testing – • Response analysis (RA) and diagnosis RA hardware – Detection vs. diagnosis – Diagnostic resolution – EBTW 2005, Tallinn, Estonia Slide 6

A Dream EBTW05 EBTW05 IC IC IC … L L L o o o g g g i i i c c c • • Components generate test patterns themselves Components generate test patterns themselves • • Test generation and application takes logarithmic time Test generation and application takes logarithmic time (e.g. 30 test vectors for 10 000 interconnect nets) (e.g. 30 test vectors for 10 000 interconnect nets) • • Testing runs at operating speed and catches dynamic defects Testing runs at operating speed and catches dynamic defects • • Components from different vendors compatibly operate Components from different vendors compatibly operate • • Diagnosis is exact and performed by components themselves Diagnosis is exact and performed by components themselves • • Simple hardware (of BS complexity) is used Simple hardware (of BS complexity) is used EBTW 2005, Tallinn, Estonia Slide 7

Introduction EBTW05 EBTW05 • Desired properties of an interconnect self-test framework: • Short test application time => using a good test set • Low hardware overhead => TG and RA must be simple • High fault coverage and relevant fault model • Aliasing-free response analysis & precise diagnosis • Compatibility with existing standards • Scalability EBTW 2005, Tallinn, Estonia Slide 8

Outline EBTW05 EBTW05 1. Introduction 2. Interconnect Faults: Models and TG Methods • Modeling of interconnect faults • Classical test generation algorithms 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Discussion EBTW 2005, Tallinn, Estonia Slide 9

Modeling of Interconnect Faults EBTW05 EBTW05 • Defect types and models • Short faults static behavior static behavior • Open faults • Delay faults • Noise/crosstalk dynamic behavior dynamic behavior • Ground bounce • … EBTW 2005, Tallinn, Estonia Slide 10

Short Faults EBTW05 EBTW05 • Possible shorts: bond wire, leg, solder, interconnect • Shorts are usually modeled as wired-AND, wired-OR faults EBTW 2005, Tallinn, Estonia Slide 11

Open Faults EBTW05 EBTW05 • Misplaced bond wire Misplaced component • Possible opens: bond wire, leg, solder, interconnect • Opens usually behave like stuck-at or delay faults EBTW 2005, Tallinn, Estonia Slide 12

Crosstalk Modeling: Noise and Skew EBTW05 EBTW05 overshoot V dd ringing delay V ss Noise-immune region Skew-immune region EBTW 2005, Tallinn, Estonia Slide 13

The Counting Sequence EBTW05 EBTW05 Open 00 00 Assume stuck-at-0 • What about 01 01 • opens? 10 10 Short 11 10 Assume wired AND • Kautz [1] showed in 1974 that a sufficient condition to detect any pair of short circuited nets was that the serial codes must be unique for all nets. Therefore the test length is ⎡ log 2 (N) ⎤ EBTW 2005, Tallinn, Estonia Slide 14

The Modified Counting Sequence EBTW05 EBTW05 Open 001 000 • Some of the Assume stuck-at-0 observed error 010 010 responses are allowed codes. • How to improve the 011 000 diagnosis? Short 100 000 Assume wired AND • All 0-s and all 1-s are forbidden codes because of open faults. Therefore the final test length is ⎡ log 2 (N+2) ⎤ • This method was proposed in 1982 by Goel & McMahon [2] EBTW 2005, Tallinn, Estonia Slide 15

The True/Complement Code EBTW05 EBTW05 Open 00 11 00 00 • All-0 and all- Assume stuck-at-0 1 codes are 01 10 01 10 not forbidden anymore! 10 01 10 00 Short 11 00 10 00 Assume wired AND • To improve the diagnostic resolution Wagner proposed the True/Complement Code in 1987 [3]. • The test length became equal 2 ⎡ log 2 (N) ⎤ EBTW 2005, Tallinn, Estonia Slide 16

The True/Complement Code EBTW05 EBTW05 Open 00 11 00 00 Assume stuck-at-0 • What about 01 10 01 10 delay faults and other dynamic 10 01 10 00 effects? Short 11 00 10 00 Assume wired AND • Important properties of the True/Complement Code are: • there are equal numbers of 0-s and 1-s upon each line • Hamming distance between any two code words is at least 2 EBTW 2005, Tallinn, Estonia Slide 17

Summary of TG Methods EBTW05 EBTW05 Counting Modified True/Compl. Walking LaMa 000 001 111 000 10000000 00001 001 010 110 001 01000000 00100 010 011 101 010 00100000 00111 011 100 100 011 00010000 01010 100 101 011 100 00001000 01101 101 110 010 101 00000100 10001 110 001 110 00000010 … 111 000 111 00000001 2 ⎡ log 2 (N) ⎤ ⎡ log 2 (3N+2) ⎤ Length ⎡ log 2 (N) ⎤ ⎡ log 2 (N+2) ⎤ N Example 14 14 28 10000 15 (N=10000) Hamming 1 1 2 2 2 distance Shorts Shorts Shorts Shorts Defects Shorts Opens Opens Opens Opens /Delays/ /Delays/ Diagnostic Bad Bad Good Good Good Properties EBTW 2005, Tallinn, Estonia Slide 18

Outline EBTW05 EBTW05 1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan • Boundary Scan • Typical test generation hardware used with BS • Handling the bus contention problem 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Discussion EBTW 2005, Tallinn, Estonia Slide 19

Boundary Scan: History EBTW05 EBTW05 • Early 1980’s – problem of test access to PCBs via “bed-of-nails” fixture • Mid 1980’s – Joint European Test Action Group (JETAG) • 1986 – US companies involved: JETAG -> JTAG • 1990 – JTAG Test Port became a standard [4]: • IEEE Std. 1149.1: Test Access Port and Boundary Scan Architecture • comprising serial data channel with a 4/5-pin interface and protocol EBTW 2005, Tallinn, Estonia Slide 20

Test Access Via Boundary Scan EBTW05 EBTW05 TDI TDI TDO TDO EBTW 2005, Tallinn, Estonia Slide 21

Test Generation Hardware EBTW05 EBTW05 • A typical TPG for the Counting Sequence [5] Code Generator (Counter or LFSR) Counter LFSR LFSR … 111 001 001 011 010 100 … Data Counter 101 011 110 010 100 111 MUX 001 101 011 100 110 101 To BS 110 111 010 Bit Select Scan Chain EBTW 2005, Tallinn, Estonia Slide 22