At-Speed BIST for Board-Level Interconnect Artur Jutman - - PowerPoint PPT Presentation

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At-Speed BIST for Board-Level Interconnect Artur Jutman

artur@pld.ttu.ee

Tallinn University of Technology, ESTONIA

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Outline

1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Summary and Discussion

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Outline

1. Introduction

• PCB testing challenges
• Characteristics and desired properties of interconnect self-test framework

2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Discussion

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PCB Testing Challenge

Challenges Challenges

• PCBs are getting complex

PCBs are getting complex

• Up to several k nets on PCB

Up to several k nets on PCB

• New faults getting involved

New faults getting involved

• Test access is getting limited

Test access is getting limited

• Workforce factors

Workforce factors How to cope? How to cope?

• ICT, X

ICT, X-

• ray, optical?

ray, optical?

• Functional testing or BIST?

Functional testing or BIST?

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Limitations of Traditional Methods

Limited interconnect fault coverage BS-compliant boards, multi-board systems, static faults only Small boards, static faults only

Board level interconnect

Not applicable at this moment Applicable as a concept only Not applicable

Network-on- Chip X-Ray & Optical Inspection Boundary Scan In-Circuit Test

Usage of traditional interconnect testing methods at different Usage of traditional interconnect testing methods at different levels of technology: levels of technology: Conclusions: Conclusions:

• dynamic fault testing is not possible with traditional methods

dynamic fault testing is not possible with traditional methods

• interconnect testing solutions for NoC are missing

interconnect testing solutions for NoC are missing

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Introduction

• Characteristics of an interconnect self-test framework:
• Test pattern generation (TPG)

–

Fault models (static vs. dynamic faults) and fault coverage

–

Deterministic, pseudo-random, and weighted sequences

–

TPG hardware

• Test application

–

Test access mechanism (BS, in-circuit test, custom solutions, etc.)

–

Test-per-scan vs. test-per-clock

–

At-speed testing vs. low-speed testing

• Response analysis (RA) and diagnosis

–

RA hardware

–

Detection vs. diagnosis

–

Diagnostic resolution

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A Dream …

IC

L

• g

i c

IC

L

• g

i c

IC

L

• g

i c

• Components generate test patterns themselves

Components generate test patterns themselves

• Test generation and application takes logarithmic time

Test generation and application takes logarithmic time (e.g. 30 test vectors for 10 000 interconnect nets) (e.g. 30 test vectors for 10 000 interconnect nets)

• Testing runs at operating speed and catches dynamic defects

Testing runs at operating speed and catches dynamic defects

• Components from different vendors compatibly operate

Components from different vendors compatibly operate

• Diagnosis is exact and performed by components themselves

Diagnosis is exact and performed by components themselves

• Simple hardware (of BS complexity) is used

Simple hardware (of BS complexity) is used

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Introduction

• Desired properties of an interconnect self-test framework:
• Short test application time => using a good test set
• Low hardware overhead => TG and RA must be simple
• High fault coverage and relevant fault model
• Aliasing-free response analysis & precise diagnosis
• Compatibility with existing standards
• Scalability

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Outline

1. Introduction 2. Interconnect Faults: Models and TG Methods

• Modeling of interconnect faults
• Classical test generation algorithms

3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Discussion

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Modeling of Interconnect Faults

• Short faults
• Open faults
• Delay faults
• Noise/crosstalk
• Ground bounce
• …

dynamic behavior dynamic behavior static behavior static behavior

• Defect types and models

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Short Faults

• Possible shorts: bond wire, leg, solder, interconnect
• Shorts are usually modeled as wired-AND, wired-OR faults

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Open Faults

• Misplaced bond wire

Misplaced component

• Possible opens: bond wire, leg, solder, interconnect
• Opens usually behave like stuck-at or delay faults

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Crosstalk Modeling: Noise and Skew

Vdd Vss

• vershoot

ringing delay Noise-immune region Skew-immune region

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The Counting Sequence

00 10 00 01 11 10 01 10

• Kautz [1] showed in 1974 that a sufficient condition to detect any pair of

short circuited nets was that the serial codes must be unique for all nets. Therefore the test length is ⎡log2(N)⎤

• What about
• pens?

Open

Assume stuck-at-0

Short

Assume wired AND

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The Modified Counting Sequence

001 000 000 010 100 011 010 000

• All 0-s and all 1-s are forbidden codes because of open faults.

Therefore the final test length is ⎡log2(N+2)⎤

• This method was proposed in 1982 by Goel & McMahon [2]
• Some of the
• bserved error

responses are allowed codes.

• How to improve the

diagnosis?

Open

Assume stuck-at-0

Short

Assume wired AND

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The True/Complement Code

00 11 10 00 00 00 01 10 11 00 10 01 01 10 10 00

• To improve the diagnostic resolution Wagner proposed the

True/Complement Code in 1987 [3].

• The test length became equal 2⎡log2(N)⎤
• All-0 and all-

1 codes are not forbidden anymore!

Open

Assume stuck-at-0

Short

Assume wired AND

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The True/Complement Code

• Important properties of the True/Complement Code are:
• there are equal numbers of 0-s and 1-s upon each line
• Hamming distance between any two code words is at least 2
• What about

delay faults and other dynamic effects?

00 11 10 00 00 00 01 10 11 00 10 01 01 10 10 00 Open

Assume stuck-at-0

Short

Assume wired AND

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Summary of TG Methods

15 10000 28 14 14 Example (N=10000) 2 2 2 1 1 Hamming distance Shorts Opens Shorts Opens /Delays/ Shorts Opens /Delays/ Shorts Opens Shorts Defects Good Good Good Bad Bad Diagnostic Properties ⎡log2(3N+2)⎤ N 2 ⎡log2(N)⎤ ⎡log2(N+2)⎤ ⎡log2(N)⎤ Length 00001 00100 00111 01010 01101 10001 … 10000000 01000000 00100000 00010000 00001000 00000100 00000010 00000001 111 000 110 001 101 010 100 011 011 100 010 101 001 110 000 111 001 010 011 100 101 110 000 001 010 011 100 101 110 111

LaMa Walking True/Compl. Modified Counting

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Outline

1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan

• Boundary Scan
• Typical test generation hardware used with BS
• Handling the bus contention problem

4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST 6. Discussion

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Boundary Scan: History

• Early 1980’s – problem of test access to PCBs via “bed-of-nails”

fixture

• Mid 1980’s – Joint European Test Action Group (JETAG)
• 1986 – US companies involved: JETAG -> JTAG
• 1990 – JTAG Test Port became a standard [4]:
• IEEE Std. 1149.1: Test Access Port and Boundary Scan

Architecture

• comprising serial data channel with a 4/5-pin interface and

protocol

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Test Access Via Boundary Scan

TDO TDO TDI TDI

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Test Generation Hardware

…

Data MUX

…

To BS Scan Chain Code Generator

(Counter or LFSR)

Bit Select Counter 001 010 011 100 101 110 111 001 100 110 111 011 101 010 111 011 101 010 001 100 110 Counter LFSR LFSR

• A typical TPG for the Counting Sequence [5]

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TPG for the Counting Sequence

• Before a test vector can be

applied it must be shifted into the BS register, which takes L clock cycles, where L is the length of the BS register

• For a test of length T the total

test application time is equal to T • L

• Moreover, the at-speed

testing is problematic here

• There is also a multiple driver

contention problem

• Drawbacks of the solution

TDO TDO TDI TDI

Analyzer Bit Select

…

Code Generator MUX

…

Counters To BS Chain

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Multiple Driver Contention Problem

A typical tri-state net in a board-level interconnect with several drivers and receivers on the same net. There is a danger of damaging the circuits when several drivers are simultaneously activated by a mistake.

3 3-

• state driver

state driver bidirectional bidirectional driver/receiver driver/receiver receiver receiver

c c

BS Chain BS Chain BS Chain BS Chain

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Solutions to the Contention Problem

• Partitioning of the generator into D-TPG & C-TPG [5-6]

D-TPG Chain Information MUX C-TPG To BS chain Select

Bit Select

…

Code Generator MUX

…

Counters D-TPG To BS Chain

• Compatible to the BS standard

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Solutions to the Contention Problem

• Partitioning of the BS Register
• Easy test application
• Good control over the bus contention issue

IC

D D-

• TDI

TDI D D-

• TDO

TDO C C-

• TDI

TDI C C-

• TD

TDO O

D-TPG Chain Information C-TPG

• - requires

additional pins and routing

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Outline

1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults

• Requirements of at-speed testing and BIST
• PRPG based TPG methods
• Crosstalk measurement
• Common drawbacks of PRPG based methods

5. Deterministic Interconnect BIST 6. Discussion

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At-Speed Interconnect Testing

0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 Some Test Pattern Generator Some Response Analyzer

• Required properties:
• Vectors should be applied in parallel (test-per-clock)
• Both 1→0 and 0→1 transitions must be activated
• Responses should be captured without delay

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Test Generation and Test Application

…

IC

L

• g

i c

TDO

inputs

• utputs

control

TDI

IC

L

• g

i c

IC

L

• g

i c

Some Test Pattern Generator Some Response Analyzer

• Test

Test-

• per

per-

• Clock instead of Test

Clock instead of Test-

• per

per-

• Scan = > BIST

Scan = > BIST

• Relevant test generation algorithm

Relevant test generation algorithm

Test Test-

• per

per-

• scan

scan Test Test-

• per

per-

• clock

clock

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At-Speed Interconnect BIST

• LFSR-MISR based solutions
• How many test

patterns are enough to cover all delay faults and other dynamic effects?

• Texas Instrument’s SCOPE library [7]
• Implemented in IBM RISC 6000 processor [8]
• LFSR optimization technique based on graph coloring and genetic search

proposed in [9].

• A modification to LFSR, which allows weighted pattern generation in [10]

0 1 1 0 0 1 1 0 0 1 1 0 LFSR MISR

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At-Speed BIST for Delays and Crosstalk

• Resembles real life interconnect switching profiles
• Worst-case interconnect switching activities without overestimation

and damaging the chip

• Designed with help of Markov chain theory
• Generation of real life switching activity [11]
• - Comparatively

high silicon area needed for TPG

• - Test sequence

might be long

• - Response

analysis is not discussed

0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 1 cascaded structure of pre- characterized nonlinear feedback shift registers Some Response Analyzer

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At-Speed BIST for Delays and Crosstalk

• Response analysis: skew and noise detection [12]

RA

ND cell SD cell FFs ND cell SD cell FFs ND cell SD cell FFs From inter- con- nect

ND cell ND cell

Signal sample Cross- coupled PMOS amplifier 1 – correct 0 – overshoot

SD cell SD cell

NOR

Signal sample Clock Pulse=error No pulse=OK Delayed & inverted clock

Vdd Vss

• vershoot

ringing delay Noise-immune region Skew-immune region

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At-Speed BIST for Delays and Crosstalk

• Alternative design of SD Cells
• - [13] is overly conservative

with the unacceptable false detection level of 40%

• - Test sequence of [14] must

be a regular clock-like signal -> bad coverage of shorts

• - [14] requires a counter and

separate sampling clock -> high hardware cost per line

• - In most cases delay

detection is enough (no need for precise measurement [14]) Double sampling data checker [12] Double sampling data checker [12]

Signal Sample Clock D D Error flag: 1 – error 0 – correct

Statistical delay measurement unit [14] Statistical delay measurement unit [14]

Sampling clock Counter Original signal Received signal Clk Cnt

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At-Speed Interconnect BIST

• Drawbacks of non-deterministic BIST solutions
• Mutual cancellation of multiple stuck-at interconnect faults has a fatal

impact on MISR’s ability to detect them (aliasing probability is very high) [15].

• Pseudo-random (PR) patterns are not optimized for specific interconnect

faults, especially dynamic ones. This has either one or another following consequence:

– The length of PR sequence necessary for sensitizing all the static and dynamic faults

might be very long.

– Defect coverage might be low [10].

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Outline

1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST

• Advantages of deterministic methods
• Shift register based TPG for ITCC code, RA
• Other Deterministic BIST Solutions

6. Discussion

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Deterministic Interconnect BIST

• Much shorter test sequences

– logarithmic in many cases – optimized accordingly to the fault model

• Explicit fault models

– provable defect detection – good diagnostic properties of the solution

• Common advantages of deterministic interconnect

BIST methods

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Deterministic Interconnect BIST

011 101 010 001 100 110 LFSR 011 101 010 001 100 110 Shift Register 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 1 1 0 1 1 1

• Circular shift register based TPG [19]

The The initial state initial state of TPG is generated by an external LFSR

• f TPG is generated by an external LFSR

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Deterministic Interconnect BIST

10 01 01 01 10 01 10 01 10 10 10 01 01 10 10 01 01 10 1 1 1 101010

• Both 1-0 and 0-1 transitions always

exist (delay fault testing)

• Both opposite value combinations

(0/1 and 1/0) appear between any two lines (crosstalk testing)

• Hamming distance between two code

words is at least 2

• Each code word consists of bit pairs

having both 0 and 1 values

• Interleaved True/Complement Code and corresponding TPG

[19]

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• On-chip at-speed response analyzer [19]

IC

RA cell RA cell RA cell RA cell RA cell RA cell

diagnostic signature

Deterministic Interconnect BIST

• Exact fault diagnosis without aliasing
• Complete testing and diagnostic solution
• Unlimited scalability and configuration independence

RA cell

Signal sample Clock (1/2 of system clock speed) D D 1 1 – error 0 – correct

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• If only fault detection is enough

Interleaved True/Complement Code & Corresponding Response Analyzer

IC

Clk D D

go/no go signal

D D

. . . . . .

Clk

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The general structure of the framework

LFSR as the feeding device for the at-speed TPG IC IC IC

…

Diagnostic Signature inputs

• utputs

control Control Signals from C-TPG

…

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At-Speed Interconnect BIST with the Interleaved True/Complement Code

• Different operation modes

inputs

• utputs

control

At At-

• Speed

Speed Testing Testing Mode Mode

IC

from previous chip to the next chip

Boundary Boundary Scan Scan Mode Mode

IC

TDI TDO

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Properties of the Solution

• Test-per-clock – allows at-speed testing
• Exact on-chip at-speed fault diagnosis
• Detection of both static and dynamic faults
• Unlimited scalability
• Configuration independence
• Compatibility with Boundary Scan standard

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Outline

1. Introduction 2. Interconnect Faults: Models and TG Methods 3. BIST for Static Faults and Boundary Scan 4. At-Speed Testing of Dynamic Faults 5. Deterministic Interconnect BIST

• Advantages of deterministic methods
• Shift register based TPG for ITCC code, RA
• Other Deterministic BIST Solutions

6. Discussion

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Deterministic Interconnect BIST

• Modification of counting and walking sequences by

replacement 0->100 and 1->011 [16]

1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 0 1 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1

• Both static and dynamic faults covered
• The main goal is to distinguish between them
• - Additional silicon

area for TPG

• - Every second

vector is repeating

• - Length is 3N and

3 ⎡log2(N)⎤

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Deterministic Interconnect BIST

• Crosstalk testing using Maximum Aggressor fault model [17]
• Best possible test for crosstalk
• Might be overly conservative however

000…000 1 000…000 111…111 111…111 000…000 1 000…000 111…111 1 111…111 111…111 111…111 000…000 000…000 i+1 …… N i 1 …… i-1 Bit Positions in the Bus

glitch test 1 glitch test 1 skew test 1 skew test 1 skew test 2 skew test 2 glitch test 2 glitch test 2

• - Quite expensive

TPG hardware: counter, decoder, FSM, and a group of 2-1 multiplexers

• - Code length is 6N

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Deterministic Interconnect BIST

• TPG based on Johnson

counters [18]

• Very cheap TPG hardware!
• Generates true/complement code of length 2N/K
• - TPG must be divided

into many separate

• parts. Each part must

be uniquely initialized.

• - Code length grows

faster than logarithmically

2N 2N

true/ true/ complement complement

0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 0 0 0 1 0 1 1 0 1 1 2N 2N 1 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 N N

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Summary

• Crosstalk testing (6N code + ND/SD cells)
• Cheap hardware (LFSR/MISR, walking, Johnson, ITCC,

ND/SD cells)

• Aliasing free diagnosis (ITCC)
• Short test sequence (ITCC, Johnson)
• Tasks and recommended methods

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Referenced and Used Materials

1. W.H. Kautz, “Testing of Faults in Wiring Interconnects,” IEEE Trans. on Computers, vol. 23, no. 4, 1974, pp. 358-363. 2.

• P. Goel and M.T. McMahon, “Electronic Chip-in-Place Test,” in Proc. of Int. Test Conf.

(ITC’82), IEEE Press, 1982, pp. 83-90. 3. P.T. Wagner, “Interconnect Testing with Boundary Scan,” in Proc. of Int. Test Conf. (ITC’87), IEEE Press, 1987, pp. 52-57. 4. IEEE 1149.1-1990, “IEEE Standard Test Access Port and Boundary-Scan Architecture,” 1990. 5. W.Feng,F.J.Meyer,F.Lombardi,“Novel control pattern generators for interconnect testing with Boundary Scan,” in Proc. Int’l Symp. Defect&Fault Tolerance in VLSI Syst., 1999, pp.112-120. 6. C.-H. Chiang and S.K. Gupta, “BIST TPG for Faults in System back-planes,” in Int. Conf.

• n Comp. Aided Design, 1997, pp. 406-413.

7.

• J. Koeter, S. Sparks, “Interconnect Testing Using BIST Embedded in IEEE 1149.1

Designs”, in Proc. of Int. ASIC Conf. , September, 1991, pp. P11-2.1- P11-2.4. 8. Chan, J. C., “An Improved Technique for Circuit Board Interconnect Test,” IEEE Trans.

• n Inst. and Meas., Vol. 41, No. 5, pp. 692-698, 1992.

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Referenced and Used Materials

9.

• C. P. Ravikumar and S. Chopra, “Testing interconnects in a system chip,” in Proc. Int.
• Conf. VLSI Design, 2000, pp. 388–391.
• 10. K. Sekar and S. Dey, “LI-BIST: A low-cost self-test scheme for SoC logic cores and

interconnects,” in IEEE VLSI Test Symp., 2002, pp. 417-422.

• 11. R. Pendurkar, A. Chatterjee, Y. Zorian, ”Switching Activity Generation with Automated

BIST Synthesis for Performance Tes-ting of Interconnects”, IEEE Trans on CAD/ICS, vol.20, no.9, 2001, pp. 1143-1158.

• 12. A. Attarha, M. Nourani, “Testing Interconnects for Noise and Skew in Gigahertz SoC”, in
• Proc. of Int. Test Conf., 2001, pp. 305-314.
• 13. Y. Zhao , S. Dey , L. Chen, “Double sampling data checking technique: an online testing

solution for multisource noise-induced errors on on-chip interconnects and buses”, in IEEE Trans on VLSI Systems, vol. 12, no. 7, July 2004, p.746-755.

• 14. C.Su, Y.T.Chen, M.J.Huang, G.N.Chen and C.L.Lee, "All Digital Built-in Delay and

Crosstalk Measurement for On-Chip Buses", in Proc. of DATE Conf., March 27-30, 2000, pp.527 - 531.

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Referenced and Used Materials

• 15. A. Hławiczka, K. Gucwa, T. Garbolino, M. Kopec, “Can a D flip-flop based MISR

compactor reliably detect interconnect faults?” in Proc. of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, April 13-16, 2005. (Artur)

• 16. C.-A. Chen, S.K. Gupta, “BIST/DFT for performance testing of bare dies and MCMs”, in
• Proc. of Electro’94, May 1994, pp. 803-812.
• 17. X. Bai, S. Dey, and J. Rajski, “Self-test methodology for at-speed test of crosstalk in chip

interconnects,” in Proc. Design Automation Conf., 2000, pp. 619–224.

• 18. T. Garbolino, A. Hławiczka, A. Kristof, “A New Idea of Test-Per-Clock Interconnect BIST

Structure”, in Proc. of East-West Design & Test Workshop (EWDTW’04), Sept, 2004, pp. 23-29.

• 19. A. Jutman, “At-Speed On-Chip Diagnosis of Board-Level Interconnect Faults”, in

Formal Proc. of 9th Euro-pean Test Symposium (ETS’04), France, May 2004, pp. 2-7.

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Materials for Further Study

• A.J.Hassan,J.Rajski,V.K.Agrawal,”Testing and Diagnosis of Interconnects using

Boundary Scan Architecture,” Proc. Int’l Test Conf., 1988, pp.126-137.

• W.T. Cheng, J.L Lewandowski, E. Wu, “Diagnosis for Wiring Interconnects,” in Proc.

ITC’90, pp. 565-571.

• E.J. Marinissen, B. Vermeulen, H. Hollmann, R.G. Bennetts, „Minimi-zing Pattern

Count for Interconnect Test under a Ground Bounce Constraint,“ in IEEE D&T of Comp., March-April 2003, pp. 8-18.

• J. Shin, H. Kim and S. Kang, “At-Speed Boundary-Scan Interconnect Testing in a

Board with Multiple System Clocks”, in Proc. Design, Automation and Test in Europe (DATE’99), pp. 473-477, 1999.

• B. Nadeau-Dostie, et. al, ”An Embedded Technique for At-Speed Interconnect

Testing,” in Proc. of Int. Test Conf., 1999, pp. 431-438.

• S.Park, T.Kim, ”A new IEEE 1149.1 boundary scan design for the detection of delay

defects,” in Proc. Design, Automation and Test in Europe (DATE’2000), pp. 458-462.

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Materials for Further Study

• C.Su, S.W.Jeng, Y.T.Chen, ”Boundary scan BIST methodology for reconfigurable

systems,” in Proc. of Int. Test Conf, 1998, pp. 774-783.

• C. Su, W. Tseng, “Configuration Free SoC Interconnect BIST Methodology”, in Proc.
• f Int. Test Conf., 2001, pp.1033-1038.
• L. Jin. “The driver/receiver conflict problem in interconnect testing with boundary-

scan,” in Proc of Asian Test Symposium (ATS’93), Beijing, China, 16-18 Nov 1993, pp. 210-214.

• A. Hassan, V. Agarwal, B. Nadeau-Dostie, and J. Rajski, “BIST of PCB interconnects

using boundary-scan architecture,” IEEE Trans. Computer-Aided Design, vol. 11, Oct. 1992, pp. 1278–1287.

• Ulf Pillkahn, “Structural test in a board self test environment,” Proc. IEEE Int. Test
• Conf. (ITC’2000), Oct 3-5, 2000, pp. 1005-1012.
• R.G. Bennetts, “Boundary Scan Tutorial” ASSET InterTech. Available from:

http://www.asset-intertech.com/login.html?doc=/PDFs/boundaryscan_tutorial.pdf

• The Boundary Scan demo applet URL:

http://www.pld.ttu.ee/dildis/automata/applets/bs/

Slide 54 EBTW 2005, Tallinn, Estonia

EBTW05 EBTW05

Thank you!