2nd Workshop on Dependable and Secure Nanocomputing Anchorage, June 27, 2008 Modeling Microprocessor Faults on High-Level Decision Diagrams R. Ubar, J.Raik, A.Jutman, M.Jenihhin Tallinn Technical University, Estonia M.Instenberg, H.-D.Wuttke Ilmenau Technical University, Germany 1 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Outline • Introduction • Motivations and contributions • Discussion: faults and tests • Fault modeling with Decision Diagrams • Modeling microprocessor faults • Experimental results • Conclusions 2 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Introduction • Fault models are needed for – test generation, – test quality evaluation and – fault diagnosis • To handle real physical defects is too difficult • The fault model should – reflect accurately the behaviour of defects, and – be computationably efficient • Usually combination of different fault models is used • Fault model free approaches (!) 3 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Introduction • Fault modeling levels – Transistor level faults – Logic level faults • stuck-at fault model Low-Level models • bridging fault model • open fault model • delay fault model – Register transfer level faults High-Level models – ISA level faults (MP faults) – SW level faults • Hierarchical fault handling • Functional fault modeling 4 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Motivations Current situation: • The efficiency of test generation (quality, speed) is highly depending on – the description method (level, language), and – fault models • Because of the growing complexity of systems, gate level methods have become obsolete • High-Level methods for diagnostic modeling are today emerging, however they are not still mature Main disadvantages: • The known methods for fault modeling are – dedicated to special classes (i.e. for microprocessors, for RTL, VHDL etc. languages...), not general – not well defined and formalized 5 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Contributions • High-Level Decision Diagrams are proposed for diagnostic modeling of digital systems • A novel DD-based node fault model is proposed • The fault model is simple and formalized • Traditional high-level fault models for different abstraction levels of digital systems can be replaced by the new uniform fault model • As the result, – the complexity of fault representation is reduced, and – the speed of test generation and fault simulation can be increased 6 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Register Level Fault Models RTL statement: K: ( If T,C) R D � F(R S1 , R S2 , … R Sm ), � N Components (variables) RT level faults: of the statement: K � K’ - label faults K - label T � T’ - timing faults T - timing condition C � C’ - logical condition faults C - logical condition R D � R D - register decoding faults R D - destination register R S � R S - data storage faults R S - source register F � F’ - operation decoding faults F - operation (microoperation) � - data transfer faults - data transfer � � N - control faults � N - jump to the next statement (F) � (F)’ - data manipulation faults 7 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Fault Models and Tests Dedicated functional fault model for multiplexer: Functional – stuck-at-0 (1) on inputs, fault model – another input (instead of, additional) – value, followed by its complement – value, followed by its complement on a line whose address differs in one bit Test description 8 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Hierarchical Fault Modeling Functions Structure Higher System level Module k W F Lower k W Sk Test System: F level W S k Bridge Fault Network of W F Network of modules k modules model W S Test Module F k ki W F k interpretation: Network of W Fki Test – at the lower level components Fault model – at the higher level W dki Component: Test Interface between levels F ki Network of transistors 9 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Logic Level Faults on SSBDDs Fault modeling on Structurally Synthesized BDDs: Path y y 1 1 x 1 x 1 1 1 activation Correct Fault signal 0 0 activation 0 x 2 x 2 x 3 x 3 x 1 1 1 � 0 x 2 3 = 1 x y 0 x 4 x 4 x 5 x 5 x 4 x 5 0 Error F ( X ) x 6 Fault x 6 x 6 x 7 x 7 x 7 Stuck-at-0 = � � � y x x ( x x x ) x x 0 0 1 2 3 4 5 6 7 10 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Data Path in Digital Systems M 1 y 1 Function Control Path M 1 = R 1 0 y 1 M 1 = IN x M 2 Function y 2 Data Path M 2 = R 1 0 M 2 = IN 1 y 1 y 2 y 3 y 4 M 3 Function y 3 a • R 1 c M 3 = M 1 + R 2 0 M 1 + M 3 = IN 1 e • M 3 = R 1 2 M 3 R 2 b • M 3 = M 2 * R 2 3 M 2 • * • R 2 IN d y 4 Operation Function 0 Reset R 2 = 0 1 Hold R 2 = R ’ 2 2 Load R 2 = M 3 11 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Decision Diagram of the Data Path M 1 R 2 0 # 0 y 1 Function y 4 M 1 = R 1 0 1 1 M 1 = IN R 2 M 1 M 2 0 0 2 Function y 2 y 3 y 1 R 1 + R 2 M 2 = R 1 0 R 2 M 2 = IN 1 1 IN + R M 3 2 1 Function y 3 IN M 3 = M 1 + R 2 0 2 M 3 = IN 1 R 1 M 3 = R 1 2 3 0 M 3 = M 2 * R 2 3 y 2 R 1 * R 2 R 2 + M 3 R 2 1 y 4 Operation Function IN* R 2 0 Reset R 2 = 0 M 2 1 Hold R 2 = R ’ 2 2 Load R 2 = M 3 12 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Faults and High-Level Decision Diagrams R 2 RTL-statement: 0 # 0 y 4 K: ( If T,C) R D � F(R S1 ,R S2 ,…R Sm ), � N 1 R 2 Terminal nodes 0 0 2 RTL-statement faults: y 3 y 1 R 1 + R 2 data storage, Nonterminal nodes 1 data transfer, RTL-statement faults: IN + R 2 data manipulation faults 1 label, IN timing condition, y 1 y 2 y 3 y 4 2 logical condition, R 1 a • R 1 register decoding, c 3 0 M 1 + operation decoding, y 2 e R 1 * R 2 • M 3 R 2 control faults • b 1 • M 2 * IN* R 2 • IN d 13 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Faults and High-Level Decision Diagrams RTL-statement: K: ( If T,C) R D � F(R S1 ,R S2 ,…R Sm ), � N Nonterminal nodes Label (decoding) Register or function RTL-statement faults: faults decoding faults Data part: label, R D timing condition, T K C F(R) logical condition, register decoding, Data transfer, storage Control part: or manipulation faults operation decoding, K NEW control faults T K C #N Terminal nodes Control (storage) RTL-statement faults: faults data storage, data transfer, Control (decoding) faults Timing faults data manipulation faults 14 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Fault Modeling on DDS Binary DD General case of DD with 2 terminal nodes and with n � 2 terminal nodes and n � 2 outputs 2 outputs from each node from each node 0 y l 0 G y Y l 1 1 G Y l 1 1 2 l m l m m m l 2 l h h l 0 l k l n l k +1 F k F n F k+1 0 15 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Fault Model for Decision Diagrams • Each path in a DD describes the behavior of the system in a specific mode of operation • The faults having effect on the behaviour can be associated with nodes along the path • A fault causes incorrect leaving the path activated by a test 16 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Fault Model for Decision Diagrams D1: the output edge for x ( m ) = i of a node m is always activated D2: the output edge for x ( m ) = i of a node m is broken D3: instead of the given edge, another edge or a set of edges is activated 17 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Microprocessor Modeling with S-Graphs Instruction set of a Microprocessor: S-Graph: I 1 : MVI A,D A � IN IN I 2 : MOV R,A R � A I 3 : MOV M,R OUT � R I 5 I 1 , I 6 I 4 : MOV M,A OUT � A I 2 I 5 : MOV R,M R � IN I 2 - I 5 I 1 , I 3 , I 4 R A I 6 : MOV A,M A � IN I 7 - I 10 I 6 - I 10 I 7 , I 8 , I 9 I 7 : ADD R A � A + R I 4 I 3 I 8 : ORA R A � A � R I 9 : ANA R A � A � R OUT A � ¬ A I 10 : CMA A,D 18 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
Test Generation for Microprocessors High-Level DDs for a microprocessor (example): DD-model of the Instruction set: 1,6 microprocessor: A I IN I 1 : MVI A,D A � IN 3 2,3,4,5 I R OUT A I 2 : MOV R,A R � A 4 I 3 : MOV M,R OUT � R 7 A + R A I 4 : MOV M,A OUT � A 8 I 5 : MOV R,M R � IN 2 A � R I A R I 6 : MOV A,M A � IN 9 A � R I 7 : ADD R A � A + R 5 IN I 8 : ORA R A � A � R 10 ¬ A I 9 : ANA R A � A � R 1,3,4,6-10 A � ¬ A I 10 : CMA A,D R 19 Tallinn University of Technology, Technical University Ilmenau, GERMANY ESTONIA
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