Flash Memory Suzhen Wu*, Sijie Lan *, Jindong Zhou*, Hong Jiang, - - PowerPoint PPT Presentation

BitFlip: A Bit-Flipping Scheme for Reducing Read Latency and Improving Reliability of Flash Memory

Suzhen Wu*, Sijie Lan*, Jindong Zhou*, Hong Jiang§, Zhirong Shen*

*Xiamen University, China §University of Texas at Arlington, USA 36th International Conference on

Massive Storage Systems and Technology (MSST 2020)

Ou Outl tline ine

• Bac

ackgro kground und an and Motivatio ivation

• Bit

itFli lip p De Desi sign gn

• Eval

aluatio uation

• concl

clus usio ion

Ho How w er errors rors occ ccur ur？

• P/E Cyclin

ing Erro rors rs

• Progr

gram am Erro rors rs

• Program

am Inter erfer erenc ence e Error

• rs
• Reten

entio ion n Error

• rs (domi

mina nant nt source e of fl flash h me memo mory ry error

• rs)
• ……

Our work focus on the Retention errors

Wh Why re y rete tention ntion er errors rors occ ccur? ur?

After multiple erase and program

• perations, the insulating property
• f tunnel oxide degrade gradually.

So, more electrons leakage happen and more retention errors occur.

Control Gate Gate Oxide Floating Gate Tunnel Oxide Drain n+ Source n+ Substrate

Wh Why re y rete tention ntion er errors rors occ ccur? ur?

Errors happen.

In MLC cell, there are four states which store four kinds of bits respectively.

ECC CC meth ethods

• ds in

in SS SSDs Ds

The figure above from the work of Zhao et al.

LDPC code tolerate more errors, but more errors cause more sensing level, which degrade performance.

LD LDPC C in in SSD SSDs

Start with hard-decision decoding (X=0) Read succeeds Decoding successes? Read fails

Yes

Yes Soft-decision decoding with level X++ No No Level X is the maximum level in soft- decision decoding ?

Ch Char aracter acterist istic ics s of

• f re

rete tentio ntion n er errors rors

Most retention errors are 00->01 (46%), 01->10 (44%). Which means, higher threshold voltages are more likely to leak charge.

The figure above from the work of Cai et al.

Fil ile e Ana naly lysis sis

In our analysis, the proportion of four kinds of states are quit different in different files.

Motiva tivation tion

• So,

, highe gher r Vth th (th thre reshold shold volt ltages) ages) means ans higher gher rete tenti tion n erro rors rs. .

• Can

n we reduce duce th the e sta tate tes s number mber with th higher gher Vth th?

• We desig

ign th the e Bi

BitFli tFlip

10 11 11 10 Data with higher Vth BitFlip 01 00 00 01 Data with lower Vth

Data store with lower Vth states means less errors will occur

character ‘a’

• Ba

Background kground and nd Mo Motiv ivati ation

• n
• Bi

BitFli lip p De Desi sign gn

• Eval

aluatio uation

• concl

nclusio usion

Ou Outl tline ine

Arc rchitecture hitecture of B f Bit itFlip Flip

• 1. BitFlip design in FTL
• 2. Bit counter module: Split a page to equal size
• units. Calculate the state's number of units to

determine which unit needs to be flipped

• 3. Reorganization module: Base on tag-bits, flip

the units which need flip, then reorganize (data store in Flash)

NAND Flash

LDPC encoder Write data Read data

Host BitFlip

LDPC decoder Bit counter module Reorganization module Write Read

FTL

Wr Write ite proces rocess

1.Bit Counter Module:

• Split page to several equal units.
• Count states’ number of each unit
• Generate tag bit of each unit to mark

whether it should be flipped

NAND Flash

LDPC encoder Write data Read data

Host BitFlip

LDPC decoder Bit counter module Reorganization module Write Read

FTL

Sum(00+01)>Sum(10+11)? Tag bit = 1 Tag bit = 0 Yes No

Unit

Count states

Bit Counter Module

For each unit

Unit Unit Unit

Wr Write ite proces rocess

2.Reorganization Module:

• Judging from tag bits, flip the units and

reorganize the units to a page.

NAND Flash

LDPC encoder Write data Read data

Host BitFlip

LDPC decoder Bit counter module Reorganization module Write Read

FTL

tag bits

512 Bytes

Generate units for bit flips

1 1 1 1

Data to be stored in flash after reorganization Reorganization Module

1111 1111 1111 1111

Rea ead d proces rocess

1.Reorganization Module:

• decoding data
• Base on tag bits, flip the units to restore
• riginal data

NAND Flash

LDPC encoder Write data Read data

Host BitFlip

LDPC decoder Bit counter module Reorganization module Write Read

FTL

……

Count states’ number 0 1 0 0 1 1 1 1 Tag bits

Bit Counter Module Reorganization Module

Reorganize

Data area Spare area

01001111

Wr Write ite

A page Flip ‘00’+’01’>’10’+’11’ ‘00’+’01’<’10’+’11’

Rea ead

Data area Spare area

01001111

Flip

host

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Backgr kground

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• n
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itFli lip p De Desi sign gn

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valuat luation ion

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Ou Outl tline ine

Eva valuat luation ion Se Setu tup p

➢ Configurations of SSD ➢ Test environment

• SSDsim Simulator
• We range the RBER from 4e-3 to 13 e-3,

➢ Test on real world files and traces files (MSR)

Red educe uce er error ror-prone prone st stat ates es

➢BitFlip can reduce about 2.3%-53.9% of the error- prone states for different file types, thereby demonstrating the effectiveness of BitFlip.

Co Comparison mparison on th n the de e deco coding ding le leve vels ls

➢where BitFlip can reduce 27.1%-31.6% of the decoding levels on average.

Co Comparison mparison on th n the rea e read d la late tency. ncy.

➢BitFlip can reduce the read latency by 25.9%-34.2% for each trace compared with the baseline approach.

The he nu number ber of P/ f P/E cy cycles cles th that at ca can be n be en endur ured. ed.

➢BitFlip can increase 2.9%-33.3% of P/E cycles that the flash memory can endure.

Su Summary mmary

➢BitFlip lip can reduce e the erro ror-pr prone

• ne st

states ➢Comp mparison ison on the de deco codi ding ng levels els

• BitFlip can reduce the decoding levels on average.

➢Comp mparison ison on the read latenc ncy.

• By reducing the error-prone states, BitFlip significantly reduce the

decoding time needed in read operations.

➢The numb mber r of P P/E cycles that can be endure red.

• BitFlip increase P/E cycles that the flash memory can endure

Thanks! Q&A

BitFlip: A Bit-Flipping Scheme for Reducing Read Latency and Improving Reliability of Flash Memory

Suzhen Wu*, Sijie Lan*, Jindong Zhou*, Hong Jiang§, Zhirong Shen*

*Xiamen University, China §University of Texas at Arlington, USA