The BIST History of FPGAs FPGAs The BIST History of The BISTory - - PowerPoint PPT Presentation

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The BIST History of The BIST History of FPGAs FPGAs

Chuck Stroud Chuck Stroud

Electrical and Computer Engineering Electrical and Computer Engineering Auburn University Auburn University

The The BISTory BISTory of

• f FPGAs

FPGAs

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Outline of Presentation Outline of Presentation

• Background

Background

• Overview of

Overview of FPGAs FPGAs & FPGA Testing & FPGA Testing

• My Experience in

My Experience in FPGAs FPGAs

• BIST Approaches for

BIST Approaches for FPGAs FPGAs

• Logic BIST Approaches

Logic BIST Approaches

• CAD Tool Features vs. Testability

CAD Tool Features vs. Testability

• Routing BIST Approaches

Routing BIST Approaches

• Other Cores & Resources

Other Cores & Resources

• Embedded Processor

Embedded Processor-

• Based BIST

Based BIST

• Summary

Summary

3

FPGA Characteristics FPGA Characteristics

• Configuration memory

Configuration memory

• 32K

32K -

• 50M bits

50M bits

• Array of Programmable Logic Blocks (

Array of Programmable Logic Blocks (PLBs PLBs) )

• 100

100 -

• 22,270

22,270 PLBs PLBs per FPGA per FPGA

• 1

1-

• 8 4

8 4-

• input

input LUTs LUTs and 1 and 1-

• 8 flip

8 flip-

• flops per PLB

flops per PLB

• Programmable interconnect network

Programmable interconnect network

• Wire segments

Wire segments

• 50

50 -

• 400 per PLB

400 per PLB

• Programmable switches

Programmable switches

• 80

80 -

• 2,400 per PLB

2,400 per PLB

• Programmable I/O cells

Programmable I/O cells

• Bi

Bi-

• direction buffer with flip

direction buffer with flip-

• flops/latches

flops/latches

• 50

50 -

• 750 per FPGA

750 per FPGA

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Important Trends in FPGAs Important Trends in FPGAs

• Dynamic partial reconfiguration

Dynamic partial reconfiguration

• Incorporating specialized cores

Incorporating specialized cores

• RAMs

RAMs -

• single

single-

• port, dual

port, dual-

• port, FIFO, ECC

port, FIFO, ECC

• 128

128 -

• 18K bits per RAM

18K bits per RAM

• 4

4 -

• 550 per FPGA

550 per FPGA

• DSPs

DSPs including multipliers, accumulators, etc. including multipliers, accumulators, etc.

• 30

30 -

• 510 per FPGA

510 per FPGA

• Embedded processor cores

Embedded processor cores

• Up to 2 hard cores per FPGA

Up to 2 hard cores per FPGA

• Also support soft processor cores synthesized in FPGA

Also support soft processor cores synthesized in FPGA

• Internal access to configuration memory

Internal access to configuration memory

• Write and read access by embedded processor core

Write and read access by embedded processor core

• FPGAs becoming more like

FPGAs becoming more like SoCs SoCs

• ASICs &

ASICs & SoCs SoCs now incorporate FPGA cores now incorporate FPGA cores

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FPGA Testing Challenges FPGA Testing Challenges

• Programmability

Programmability

• Must test all modes of operation

Must test all modes of operation

• Architectures designed for applications

Architectures designed for applications

• Testing issues/problems left to product/test engineers

Testing issues/problems left to product/test engineers

• CAD tools designed for high

CAD tools designed for high-

• level synthesis

level synthesis

• Do not support control of proper test conditions

Do not support control of proper test conditions

• Constantly growing sizes

Constantly growing sizes

• Reconfiguration dominates test time

Reconfiguration dominates test time

• Constantly changing architectures

Constantly changing architectures

• Architectural features/limitations directly affect

Architectural features/limitations directly affect testability and test development testability and test development

• Incorporation of many new/different cores

Incorporation of many new/different cores

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FPGA Testing FPGA Testing

• Typically partitioned for logic and routing

Typically partitioned for logic and routing

• But both resources needed to test each other

But both resources needed to test each other

• External testing

External testing

• Good for manufacture testing only

Good for manufacture testing only

• Tests applied via I/O pins

Tests applied via I/O pins

• Package dependent and limited by I/O pins

Package dependent and limited by I/O pins

• Boundary Scan (only with INTEST)

Boundary Scan (only with INTEST)

• Extremely long test time

Extremely long test time

• Internal Testing (BIST)

Internal Testing (BIST)

• Good for manufacturing & system

Good for manufacturing & system-

• level test

level test

• Good for embedded FPGA cores

Good for embedded FPGA cores

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FPGA Testing FPGA Testing

• Application independent testing

Application independent testing

• Test all resources in FPGA

Test all resources in FPGA

• Good for manufacturing testing

Good for manufacturing testing

• Requires

Requires many many test configurations test configurations

• Long test time

Long test time -

• downloads dominate test time

downloads dominate test time

• No area/performance penalty in system

No area/performance penalty in system

• Application specific testing

Application specific testing

• Test only resources used by system function

Test only resources used by system function

• Requires fewer configurations

Requires fewer configurations

• But requires new tests for new applications

But requires new tests for new applications

• Good for system

Good for system-

• level testing only

level testing only

• Area/performance penalty for test circuitry

Area/performance penalty for test circuitry

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System System-

• Level FPGA Testing

Level FPGA Testing

• System

System-

• level test of FPGA

level test of FPGA-

• based designs

based designs

• Diagnostic software for test in system mode

Diagnostic software for test in system mode

• Many months of diagnostic code development

Many months of diagnostic code development

• Good diagnostic resolution difficult to achieve

Good diagnostic resolution difficult to achieve

• DFT/BIST in FPGA (for system

DFT/BIST in FPGA (for system-

• level test)

level test)

• Area penalty typically 10

Area penalty typically 10-

• 30%

30%

• Performance penalty typically 2

Performance penalty typically 2-

• 3 gate delays

3 gate delays

• Less logic for system function

Less logic for system function

• Longer design time

Longer design time

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BIST for BIST for FPGAs FPGAs

• Basic idea:

Basic idea: reprogram FPGA to test itself reprogram FPGA to test itself

• BIST logic disappears after test

BIST logic disappears after test

• No area overhead or performance penalties

No area overhead or performance penalties

• Applicable to all levels of testing

Applicable to all levels of testing

• Application independent testing

Application independent testing

• A generic test for a generic component

A generic test for a generic component

• Good diagnostic resolution

Good diagnostic resolution

• To faulty PLB or wire segment/switch within FPGA

To faulty PLB or wire segment/switch within FPGA

• No diagnostic code development or DFT design

No diagnostic code development or DFT design

• Cost:

Cost:

• Memory to store BIST configurations

Memory to store BIST configurations

• Goal:

Goal: minimize number of configurations minimize number of configurations

• Download time to execute BIST configurations

Download time to execute BIST configurations

• Goal:

Goal: minimize downloads minimize downloads

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My BIST & FPGA Background My BIST & FPGA Background

• Bell Labs (1977

Bell Labs (1977-

• 93)

93)

• Telecommunications systems

Telecommunications systems

• I designed

I designed

• 21 production VLSI devices

21 production VLSI devices

• Prototype boards for over half of these

Prototype boards for over half of these

• 3 production printed circuit boards

3 production printed circuit boards

• 1981

1981 -

• began work on BIST

began work on BIST

• Most VLSI devices included BIST

Most VLSI devices included BIST

• 1984

1984 -

• began work on

began work on FPGAs FPGAs

• 1985

1985 -

• began work on synthesis tools

began work on synthesis tools

• 1987

1987 -

• first mixed

first mixed-

• signal BIST

signal BIST

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Initial Work on Initial Work on FPGAs FPGAs

• Bread board

Bread board ASICs ASICs in design methodology in design methodology

• We used TTL and fused

We used TTL and fused-

• based

based PALs PALs in early 1980s in early 1980s

• I designed RAM

I designed RAM-

• based programmable device in 1984

based programmable device in 1984

• Soft Programmable Logic Array Technology (SPLAT)

Soft Programmable Logic Array Technology (SPLAT)

• My original idea of BIST for

My original idea of BIST for FPGAs FPGAs: :

• program for

program for “ “easier easier” ” testing testing

• Needed synthesis tool to program SPLAT

Needed synthesis tool to program SPLAT

• Began development of CONES in 1985

Began development of CONES in 1985

• Synthesized behavioral models written in C to

Synthesized behavioral models written in C to

• Standard cell based

Standard cell based ASICs ASICs

• PLD

PLD-

• based bread boards and PCBs

based bread boards and PCBs

• Used 22V10s and 16V8s and considered use of Xilinx LCA

Used 22V10s and 16V8s and considered use of Xilinx LCA

• Refined idea of BIST for

Refined idea of BIST for FPGAs FPGAs: :

• program for BIST and diagnosis

program for BIST and diagnosis – – can route around faults can route around faults

• CONES became a design methodology

CONES became a design methodology

• Widely used at Bell Labs until early 1990s (then VHDL)

Widely used at Bell Labs until early 1990s (then VHDL)

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BIST for BIST for FPGAs FPGAs

• Started actual work on BIST for

Started actual work on BIST for FPGAs FPGAs in 1993 in 1993

• No one had done it (

No one had done it (nothing in literature nothing in literature) )

• Good area for academic R&D starting at Univ. of

Good area for academic R&D starting at Univ. of Ky Ky

• Off

Off-

• line BIST and diagnosis of

line BIST and diagnosis of FPGAs FPGAs

• Funded by Bell Labs, NSF & UK CRMS (1993

Funded by Bell Labs, NSF & UK CRMS (1993-

• 1998)

1998)

• ORCA 2C and 2CA series

ORCA 2C and 2CA series

• Also some preliminary BIST work for ORCA 3C and 4 series

Also some preliminary BIST work for ORCA 3C and 4 series

• Miron

Miron Abramovici Abramovici at Bell Labs joined me in 1994 at Bell Labs joined me in 1994

• Expertise in ATPG, DFT, and diagnosis of

Expertise in ATPG, DFT, and diagnosis of ASICs ASICs

• On

On-

• line BIST, diagnosis, and fault

line BIST, diagnosis, and fault-

• tolerance

tolerance

• Funded by DARPA and

Funded by DARPA and Lucent Lucent→ →Agere Agere (1997 (1997 -

• 2001)

2001)

• Used ORCA 2C/2CA due to dynamic partial reconfiguration

Used ORCA 2C/2CA due to dynamic partial reconfiguration

• Considered Xilinx 6800 series

Considered Xilinx 6800 series

• John

John Emmert Emmert joined myself and joined myself and Miron Miron Abramovici Abramovici in 1999 in 1999

• Expertise in fault

Expertise in fault-

• tolerant approaches in

tolerant approaches in FPGAs FPGAs

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More BIST for More BIST for FPGAs FPGAs

• Manufacturing test development and BIST

Manufacturing test development and BIST

• Funded by Cypress & UK CRMS (1997

Funded by Cypress & UK CRMS (1997– –2000) 2000)

• Cypress Delta 39K series

Cypress Delta 39K series

• Some initial work on 37K series

Some initial work on 37K series CPLDs CPLDs

• Included (besides logic and routing)

Included (besides logic and routing)

• BIST for embedded

BIST for embedded RAMs RAMs and and FIFOs FIFOs

• Embedded logic analyzer

Embedded logic analyzer

• Similar to Xilinx

Similar to Xilinx ChipScope ChipScope

• Embedded processor

Embedded processor-

• based BIST

based BIST

• Funded by NSA & US Army SMDC (2003

Funded by NSA & US Army SMDC (2003-

• 2006)

2006)

• Atmel AT94K series FPSLIC

Atmel AT94K series FPSLIC

• Also applicable to AT40K series FPGA

Also applicable to AT40K series FPGA

• Included (besides logic and routing)

Included (besides logic and routing)

• BIST for embedded

BIST for embedded RAMs RAMs and I/O buffers and I/O buffers

• Guard bands and fail

Guard bands and fail-

• silent operation

silent operation

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BIST for Xilinx BIST for Xilinx FPGAs FPGAs

• 4000 & Spartan series

4000 & Spartan series

• Funded by NSA & NC Space Consortium (2001

Funded by NSA & NC Space Consortium (2001-

• 2003)

2003)

• 4000E, 4000XL/XLA, Spartan

4000E, 4000XL/XLA, Spartan

• BIST for logic and routing resources

BIST for logic and routing resources

• Virtex

Virtex-

• I,

I, Virtex Virtex-

• II Pro, Spartan

II Pro, Spartan-

• II, Spartan

II, Spartan-

• 3

3

• Funded by NSA (2004

Funded by NSA (2004-

• 2005)

2005)

• Preliminary work in

Preliminary work in

• BIST and diagnosis

BIST and diagnosis

• Logic, routing, I/O buffers, embedded

Logic, routing, I/O buffers, embedded RAMs RAMs, multipliers , multipliers

• Dynamic partial reconfiguration

Dynamic partial reconfiguration

• Partial configuration memory read back

Partial configuration memory read back

• Guard bands and fail

Guard bands and fail-

• silent operation

silent operation

• Embedded processor

Embedded processor-

• based BIST for

based BIST for Virtex Virtex-

• II Pro

II Pro

• Virtex

Virtex-

• 4

4

• Funded by NSA (2005

Funded by NSA (2005-

• 2006)

2006)

• BIST for logic, routing, I/O buffers,

BIST for logic, routing, I/O buffers, RAMs RAMs, , DSPs DSPs

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Our FPGA BIST Configurations Our FPGA BIST Configurations

152 152 128 128 12 12 4000E/Spartan 4000E/Spartan 230 230 206 206 12 12 4000XL/XLA 4000XL/XLA 307 307 283 283 12 12 Virtex Virtex-

• I/Spartan

I/Spartan-

• II

II 64 64 56 56 4 4 AT94K/40K AT94K/40K Atmel Atmel 459 459 419 419 20 20 39K 39K Cypress Cypress Xilinx Xilinx ORCA ORCA FPGA FPGA ? ? 76 76 66 66 Total Total ? ? 15 15 Virtex Virtex-

• 4

4 48 48 14 14 2CA 2CA 27 (48) 27 (48) 9 9 2C 2C Routing Routing Logic Logic

Notes: Logic BIST configurations are applied 2 times Configurations for embedded cores not included

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Other Work in FPGA Testing Other Work in FPGA Testing

• Lombardi & Huang

Lombardi & Huang

• External testing of logic and routing

External testing of logic and routing

• Xilinx 4000 and

Xilinx 4000 and Altera Altera

• Renovell

Renovell and and Zorian Zorian (with others) (with others)

• Test configurations for logic and routing

Test configurations for logic and routing

• Xilinx 4000 and ORCA

Xilinx 4000 and ORCA

• Harris and

Harris and Tessier Tessier

• BIST configurations for routing

BIST configurations for routing

• Xilinx 4000 and

Xilinx 4000 and Virtex Virtex

• Sun and Chan

Sun and Chan

• Parity

Parity-

• based BIST for routing

based BIST for routing

• Xilinx 4000

Xilinx 4000

• Tahoori

Tahoori

• Application dependent testing of logic and routing

Application dependent testing of logic and routing

• Xilinx

Xilinx Virtex Virtex

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First Logic BIST Approach First Logic BIST Approach

O TPG TPG TPG BUT BUT BUT BUT BUT BUT BUT BUT LUT LUT FF FF ORA ORA LUT LUT FF FF ORA ORA

... ... ... ...

BIST BIST start start pass/fail pass/fail

.. .

C+1 C+1 m m O O O

• Schematic entry difficult

Schematic entry difficult

• Manual placement needed to test all

Manual placement needed to test all PLBs PLBs

• Routing difficult with larger

Routing difficult with larger N Nx xN N arrays arrays

• Routing complexity =

Routing complexity = O O( (N N2

2)

)

• Global routing resources heavily used

Global routing resources heavily used

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Second Logic BIST ( Second Logic BIST (Iterative Logic Array

Iterative Logic Array)

)

BUTs BUTs BUTs BUTs Helpers Helpers Helpers Helpers TPG(s) ORA ORA BUTs BUTs BUTs BUTs Helpers Helpers Helpers Helpers TPG(s) ORA ORA BUTs BUTs Helpers unused PLBs Helpers TPG ORA

BUT BUT

helper helper ILA cell ILA cell

BUT BUT

helper helper ILA ILA cell cell

BUT BUT

helper helper ILA cell ILA cell

ORA ORA from other ILA from other ILA global routing global routing local local routing routing local local routing routing TPG TPG

• Advantages:

Advantages:

• Linear routing complexity

Linear routing complexity

• Easily scaleable

Easily scaleable

• Algorithmic PLB placement & routing with NCL

Algorithmic PLB placement & routing with NCL

• Disadvantages:

Disadvantages:

• 3 test sessions

3 test sessions

• Difficult to propagate test patterns through

Difficult to propagate test patterns through BUTs BUTs

• Particularly for sequential logic functions

Particularly for sequential logic functions

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Third Logic BIST ( Third Logic BIST (Hybrid

Hybrid)

)

TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT

Two test sessions

Row or column orientation

Good balance of global & local routing Algorithmic placement & routing with NCL

Easily scalable Good for dynamic partial reconfiguration

=TPG =TPG =BUT =BUT =ORA =ORA

Test Session 1 Test Session 1 Test Session 2 Test Session 2

TPG TPG TPG TPG BUT BUT BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA

Local Local routing routing Global routing Global routing Global routing Global routing Local Local routing routing

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BISTory BISTory of the ORA (

• f the ORA (BISTora

BISTora) )

• ORAs

ORAs impact BIST architecture impact BIST architecture

• Both logic and routing BIST

Both logic and routing BIST

• ORA design has had big impact on history of

ORA design has had big impact on history of BIST for BIST for FPGAs FPGAs

• Greater than

Greater than TPGs TPGs

• A history of

A history of ORAs ORAs in BIST for in BIST for FPGAs FPGAs could take a most of a seminar by itself could take a most of a seminar by itself

• But I don

But I don’ ’t want to BORA you!!! t want to BORA you!!!

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Latest Logic BIST ( Latest Logic BIST (Circular

Circular)

)

• Circular comparison of

Circular comparison of BUTs BUTs

• Better diagnostic resolution

Better diagnostic resolution

• Possibly better fault detection

Possibly better fault detection

• Need

Need TPGs TPGs

• Embedded processor

Embedded processor

• Other cores

Other cores

• DSP

DSP

• Embedded RAM

Embedded RAM

• DSP counter reads

DSP counter reads

• RAM (ROM) with test patterns

RAM (ROM) with test patterns

• Need sufficient routing resources

Need sufficient routing resources

• Available in many newer

Available in many newer FPGAs FPGAs

=TPG =TPG =BUT =BUT =ORA =ORA

Test Session #1 Test Session #2

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Logic BIST for Large Logic BIST for Large FPGAs FPGAs

• Need to manage

Need to manage loading on loading on TPGs TPGs

• Signals degrade

Signals degrade completely after 200 completely after 200 PIPs PIPs

• Quad BIST structures

Quad BIST structures in large arrays in large arrays

• Small number of rows

Small number of rows with BIST structure with BIST structure across all columns across all columns

• Repeat to fill array

Repeat to fill array

TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA TPG TPG BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA BUT BUT ORA ORA

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Other Logic BIST Approaches Other Logic BIST Approaches

• Ping

Ping-

• Pong (BIST)

Pong (BIST)

• One test session by combining

One test session by combining TPGs TPGs & & BUTs BUTs

• FSM approach with current state as test patterns

FSM approach with current state as test patterns

• No

No ORAs ORAs

• Config

Config memory memory readback readback every BIST clock cycle every BIST clock cycle

• Only tests

Only tests LUTs LUTs and Flip and Flip-

• flops

flops

• More

More reconfigs reconfigs in one test session in one test session

• BORA

BORA-

• BORA (Tahitian BIST)

BORA (Tahitian BIST)

• One test session by combining

One test session by combining BUTs BUTs & & ORAs ORAs

• No

No TPGs TPGs

• Test patterns from embedded processor

Test patterns from embedded processor

• Only tests

Only tests LUTs LUTs and and FFs FFs

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CAD Tool Features vs. Testability CAD Tool Features vs. Testability

• Controlling test conditions with CAD tools

Controlling test conditions with CAD tools

• Oriented for design

Oriented for design

• Oriented for synthesis

Oriented for synthesis

• For testing we need to:

For testing we need to:

• Control unselected inputs to logic multiplexers

Control unselected inputs to logic multiplexers

• Test for stuck

Test for stuck-

• at faults

at faults

• Control opposite logic values on at least one

Control opposite logic values on at least one unselected input for MUX unselected input for MUX PIPs PIPs

• Test for PIP stuck

Test for PIP stuck-

• on faults
• n faults
• # test configurations = # MUX inputs

# test configurations = # MUX inputs

• DRC complaints about antennas & stubs

DRC complaints about antennas & stubs

• Delete signals for test conditions

Delete signals for test conditions

A S B Z

x sa1

1 1/0 1/0

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Logic BIST Place & Route Logic BIST Place & Route

PAR Routing PAR Routing Our Routing Heuristics Our Routing Heuristics

• Problem:

Problem: PAR re PAR re-

• maps

maps BUT configurations BUT configurations

• Supposedly improves routability

Supposedly improves routability

• Destroys test conditions for fault

Destroys test conditions for fault detection detection

• Solution:

Solution: Develop our own Develop our own routing heuristics in C routing heuristics in C program for logic BIST program for logic BIST

• Maintains test conditions

Maintains test conditions

• Faster clock frequencies

Faster clock frequencies

• Longer BIST development time

Longer BIST development time

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NCL NCL-

• XDL Example for ORA

XDL Example for ORA

LUT G BLO1 BRO1 BLO2 BRO2 LUT F BLO3 BRO3 BLO4 BRO4 LUT H YQ

inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 , inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 , cfg " cfg "F::#LUT:F=(F1@F2)+(F3@F4) F::#LUT:F=(F1@F2)+(F3@F4) F4MUX::F4I F4MUX::F4I G::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2I G::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2I H::#LUT:H=F+G+H1 H0::G H1::C4 H::#LUT:H=F+G+H1 H0::G H1::C4 H2::F H2::F CLKY::CLK CLKY::CLK DY::H DY::H YQMUX::QY SRY::RESET YQMUX::QY SRY::RESET FFY::#FF FFY::#FF SRX::RESET FFX::#FF " ; SRX::RESET FFX::#FF " ; net "ora_1_1_yq" , net "ora_1_1_yq" ,

• utpin "ora_1_1" YQ ,
• utpin "ora_1_1" YQ ,

inpin "ora_1_1" C4 , inpin "ora_1_1" C4 , pip R1C1 CENTER_GYQ pip R1C1 CENTER_GYQ -

• > CENTER_GYQ_VERT ,

> CENTER_GYQ_VERT , pip R1C1 CENTER_GYQ_VERT pip R1C1 CENTER_GYQ_VERT -

• > CENTER_H2R ,

> CENTER_H2R , pip R1C1 CENTER_H2R pip R1C1 CENTER_H2R -

• > CENTER_C4 ,

> CENTER_C4 , ; ; routed net in XDL inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 , inst "ora_1_1" "CLB" , placed R1C1 CLB_R1C1 , cfg " cfg "F::#LUT:F=(F1@F2)+(F3@F4) F::#LUT:F=(F1@F2)+(F3@F4) F4MUX::F4I F4MUX::F4I G::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2I G::#LUT:G=(G1@G2)+(G3@G4) G3MUX::G3I G2MUX::G2I H::#LUT:H=F+G+H1 H0::G H1::C4 H::#LUT:H=F+G+H1 H0::G H1::C4 H2::F H2::F CLKY::CLK CLKY::CLK DY::H DY::H YQMUX::QY SRY::RESET YQMUX::QY SRY::RESET FFY::#FF FFY::#FF SRX::RESET FFX::#FF " ; SRX::RESET FFX::#FF " ; net "ora_1_1_yq" , net "ora_1_1_yq" ,

• utpin "ora_1_1" YQ ,
• utpin "ora_1_1" YQ ,

inpin "ora_1_1" C4 , inpin "ora_1_1" C4 , ; ; unrouted net in XDL

27

Automated BIST Configurations Automated BIST Configurations

• C program generates

C program generates .XDL file .XDL file

• .XDL converted to .NCD

.XDL converted to .NCD

• xld

xld – –xdl2ncd xdl2ncd bist.ncd bist.ncd

• FPGA Editor

FPGA Editor

• Design Rule Check

Design Rule Check

• Route

Route

• “

“no pin swap no pin swap” ” option

• ption
• .NCD converted to .BIT

.NCD converted to .BIT file to download into file to download into FPGA for BIST FPGA for BIST

FPGA Editor FPGA Editor BIST Program BIST Program

FPGA FPGA

BITgen.exe BITgen.exe BIT file BIT file XDL file XDL file NCD file NCD file XDL.exe XDL.exe

download

28

Programmable Routing Network Programmable Routing Network

• Wire segments of varying length

Wire segments of varying length

• x

xN N = = N N PLBs PLBs in length in length

• N

N = 1, 2, 4, 6 are common = 1, 2, 4, 6 are common

• xH

xH = half the array in length = half the array in length

• xL

xL = length of full array = length of full array

• Programmable Interconnect Points (

Programmable Interconnect Points (PIPs PIPs) )

• Also known as Configurable Interconnect Points (

Also known as Configurable Interconnect Points (CIPs CIPs) )

• Transmission gate connects to 2 wire segments

Transmission gate connects to 2 wire segments

• Controlled by configuration memory bit

Controlled by configuration memory bit

• 0 = wires disconnected

0 = wires disconnected

• 1 = wires connected

1 = wires connected

config bit Wire A Wire B

29

PIPs PIPs

• Break

Break-

• point PIP

point PIP

• Connect or isolate 2 wire segments

Connect or isolate 2 wire segments

• Cross

Cross-

• point PIP

point PIP

• 2 nets straight through

2 nets straight through

• 1 net turns corner and/or fans out

1 net turns corner and/or fans out

• Compound cross

Compound cross-

• point PIP

point PIP

• Collection of 6 break

Collection of 6 break-

• point

point PIPs PIPs

• Can route to two isolated signal nets

Can route to two isolated signal nets

• Multiplexer PIP

Multiplexer PIP

• Directional and buffered

Directional and buffered

• Select 1

Select 1-

• of
• f-
• N

N inputs for output inputs for output

• Non

Non-

• decoded MUX PIP

decoded MUX PIP – – 1 1 config config bit per input bit per input

• Decoded MUX PIP

Decoded MUX PIP – – N N config config bits select from 2 bits select from 2N

N inputs

inputs

• Major routing resource in new

Major routing resource in new FPGAs FPGAs

30

Routing BIST Routing BIST

• Program

Program PLBs PLBs as as TPGs TPGs and and ORAs ORAs

• Like in logic BIST

Like in logic BIST

• Program groups of wires under test

Program groups of wires under test

• Wire segments

Wire segments

• Programmable Interconnect Points

Programmable Interconnect Points

• Tests partitioned for local and global routing

Tests partitioned for local and global routing resources resources

• Must route through

Must route through PLBs PLBs for local routing for local routing

• Fault models

Fault models

• Bridging faults and opens in wire segments

Bridging faults and opens in wire segments

• Line stuck

Line stuck-

• at faults

at faults

• Shorts to

Shorts to Vdd Vdd and and Vss Vss

• PIPs

PIPs stuck stuck-

• on and stuck
• n and stuck-
• off
• ff
• Test conditions

Test conditions

• Opposite logic values on wires/

Opposite logic values on wires/PIPs PIPs

• Monitor both logic values

Monitor both logic values

TPG ORA PLB

31

First Routing BIST Approach First Routing BIST Approach

• Originally thought logic BIST would

Originally thought logic BIST would test routing resources test routing resources

• Not true (only 55% in ORCA)

Not true (only 55% in ORCA)

• Comparison

Comparison-

• based

based

• ORAs

ORAs compare two groups of compare two groups of WUTs WUTs

• Similar to logic BIST

Similar to logic BIST

• Tried to test as much routing as

Tried to test as much routing as possible at one time possible at one time

• Poor diagnostic resolution

Poor diagnostic resolution

• Difficult to develop configurations

Difficult to develop configurations

comparison comparison-

• based ORA

based ORA

WUTs WUTs TPG TPG ORA ORA

32

Second Routing BIST Second Routing BIST

• Developed during on

Developed during on-

• line BIST project

line BIST project

• Testing restricted to routing resources

Testing restricted to routing resources for 2 rows or columns of for 2 rows or columns of PLBs PLBs

• Small Self

Small Self-

• Test

Test AReas AReas ( (STARs STARs) )

• Comparison

Comparison-

• based BIST

based BIST

• Applied to off

Applied to off-

• line BIST

line BIST

• Fill FPGA with

Fill FPGA with STARs STARs

• Tests run concurrently

Tests run concurrently

• Diagnostic resolution to STAR

Diagnostic resolution to STAR

• Easier BIST development

Easier BIST development

• But more BIST configurations

But more BIST configurations

• 27 vs. 48 for ORCA 2C

27 vs. 48 for ORCA 2C

STAR STAR

WUTs WUTs TPG TPG ORA ORA

FPGA

T T O O T T O O T T O O T T O O T T O O

33

Other Routing BIST Approaches Other Routing BIST Approaches

• Parity

Parity-

• based

based (Sun and Chan)

(Sun and Chan)

• Xilinx 4000

Xilinx 4000

• Parity bit routed over fault

Parity bit routed over fault-

• free resources

free resources

• What is fault

What is fault-

• free until you

free until you’ ’ve tested it? ve tested it?

• Harris and

Harris and Tessier Tessier

• Used our comparison

Used our comparison-

• based approach

based approach

• Pointed out 2

Pointed out 2-

• testing requirement

testing requirement

• Renovell

Renovell and and Zorian Zorian

• Minimum test configurations for switch boxes

Minimum test configurations for switch boxes

• Modified parity

Modified parity-

• based approach

based approach

parity parity-

• based ORA

based ORA

WUTs WUTs parity parity bit bit TPG TPG ORA ORA

34

Latest Routing BIST Latest Routing BIST

• Comparison

Comparison-

• based BIST

based BIST

• No good for small

No good for small PLBs PLBs and difficult to route and difficult to route

• Modified parity

Modified parity-

• based approach

based approach

• N

N-

• bit up

bit up-

• counter with even parity,

counter with even parity, and and

• N

N-

• bit down

bit down-

• counter with odd parity

counter with odd parity

• Gives opposite logic values for

Gives opposite logic values for

• Stuck

Stuck-

• on
• n PIPs

PIPs & bridging faults & bridging faults

• Parity used as test pattern

Parity used as test pattern

• N

N+1 wires under test +1 wires under test

• Good for small

Good for small PLBs PLBs

• Make

Make STARs STARs as small as possible as small as possible

CO CO

Pass/Fail Pass/Fail

O O R R A A

WUTs WUTs

TPG TPG

Cn Cn Par Par

+

35

Our FPGA BIST Configurations Our FPGA BIST Configurations

152 152 128 128 12 12 4000E/Spartan 4000E/Spartan 230 230 206 206 12 12 4000XL/XLA 4000XL/XLA 307 307 283 283 12 12 Virtex Virtex-

• I/Spartan

I/Spartan-

• II

II 64 64 56 56 4 4 AT94K/40K AT94K/40K Atmel Atmel 459 459 419 419 20 20 39K 39K Cypress Cypress Xilinx Xilinx ORCA ORCA FPGA FPGA ? ? 76 76 66 66 Total Total ? ? 15 15 Virtex Virtex-

• 4

4 48 48 14 14 2CA 2CA 27 (48) 27 (48) 9 9 2C 2C Routing Routing Logic Logic

Notes: Logic BIST configurations are applied 2 times Configurations for embedded cores not included

36

Comparing Comparing FPGAs FPGAs

• Routing BIST

Routing BIST

• Routing resources per PLB

Routing resources per PLB

• 4000XL/XLA has 25% more than ORCA 2C/2CA

4000XL/XLA has 25% more than ORCA 2C/2CA

• ORCA 2C/2CA has 48% more than 4000E/Spartan

ORCA 2C/2CA has 48% more than 4000E/Spartan

• Routing BIST configurations

Routing BIST configurations

• 206 for 4000XL/XLA

206 for 4000XL/XLA

• 48 for ORCA 2C/2CA

48 for ORCA 2C/2CA

• 128 for 4000E/Spartan

128 for 4000E/Spartan

• Number and size of multiplexer

Number and size of multiplexer PIPs PIPs

• N

N=5 for ORCA 2C multiplexer =5 for ORCA 2C multiplexer PIPs PIPs

• N

N=35 for 4000XL/XLA multiplexer =35 for 4000XL/XLA multiplexer PIPs PIPs

• Bad News:

Bad News: more & larger MUX more & larger MUX PIPs PIPs in new in new FPGAs FPGAs

• Even more routing BIST configurations

Even more routing BIST configurations

37

Comparing Routing Architectures Comparing Routing Architectures

• PLB input/output access to busses

PLB input/output access to busses

• More difficulty routing to/from wires = more

More difficulty routing to/from wires = more configs configs

• Shared vs. dedicated busses to each PLB

Shared vs. dedicated busses to each PLB

• Routing conflicts from TPGs to ORAs = more

Routing conflicts from TPGs to ORAs = more configs configs

long lines long lines by by-

• 1 lines

1 lines by by-

• 4 lines

4 lines

SB SB SB SB

FGC1 FGC2 FGC3 FGC4 X/XQ Y/YQ

Xilinx Xilinx

F1-4 G1-4 C1-4 O1-4

ORCA ORCA

repeaters repeaters

Atmel Atmel

38

Current R&D Current R&D

• Use embedded processor core to

Use embedded processor core to

• Reconfigure FPGA for BIST

Reconfigure FPGA for BIST

• Execute BIST and retrieve BIST results

Execute BIST and retrieve BIST results

• Perform diagnostic procedure

Perform diagnostic procedure

• Perform fault injection emulation

Perform fault injection emulation

• Methodical verification of BIST configurations

Methodical verification of BIST configurations

• Processor must access configuration memory

Processor must access configuration memory

• Configuration memory read very helpful

Configuration memory read very helpful

• Implemented in Atmel AT94K

Implemented in Atmel AT94K

• 8

8-

• bit AVR microcontroller

bit AVR microcontroller

• Configuration memory write access only

Configuration memory write access only

• Currently implementing in Virtex

Currently implementing in Virtex-

• 4 for NSA

4 for NSA

• PowerPC (hard core) &

PowerPC (hard core) & MicroBlaze MicroBlaze (soft core) (soft core)

• Configuration memory write and read access

Configuration memory write and read access

39

Logic BIST Architecture Logic BIST Architecture -

• Virtex

Virtex II Pro II Pro

Logic BIST Logic BIST Circuitry Circuitry Embedded Embedded Processor Processor

• 4 Test Sessions

4 Test Sessions

• Right Half

Right Half – – East & West East & West

• Left Half

Left Half – – East & West East & West

• Circular comparison for

Circular comparison for better diagnosis better diagnosis

• TPG incorporated in the

TPG incorporated in the processor half of FPGA processor half of FPGA

• Replace TPG column with

Replace TPG column with ORAs ORAs

• Extra routing needed for

Extra routing needed for BUT BUT-

• to

to-

• ORA connections

ORA connections at edge at edge

40

Test Time Results for AT94K Test Time Results for AT94K

182.4 182.4 0.110 sec 0.110 sec 20.064 sec 20.064 sec Download Download 0.075 0.075 0.343 sec 0.343 sec 0.026 sec 0.026 sec Execution Execution 76.0 76.0 0.101 sec 0.101 sec 7.680 sec 7.680 sec Download Download 0.2 0.2 0.085 sec 0.085 sec 0.016 sec 0.016 sec Execution Execution 43.5 43.5 0.639 sec 0.639 sec 27.786 sec 27.786 sec Total Test Time Total Test Time 20.090 sec 20.090 sec 7.696 sec 7.696 sec Download Download 0.453 sec 0.453 sec 0.186 sec 0.186 sec Processor Processor 44.3 44.3 Total time Total time Routing Routing BIST BIST 41.4 41.4 Total time Total time Logic Logic BIST BIST Speed Speed-

• up

up Function Function Resource Resource

• 60 BIST configurations

60 BIST configurations

• Maximum download clock frequency = 1MHz

Maximum download clock frequency = 1MHz

• Maximum processor clock frequency = 25 MHz

Maximum processor clock frequency = 25 MHz

41

Memory Reduction Results Memory Reduction Results

• Download approach needs 3.5

Download approach needs 3.5 Mbyte Mbyte for storage for storage

• Requires external control for BIST and diagnosis

Requires external control for BIST and diagnosis

• Processor

Processor-

• generated BIST program

generated BIST program

• Includes all control and diagnostic routines

Includes all control and diagnostic routines

• Will fit in program memory of embedded processor

Will fit in program memory of embedded processor

• Or can be easily downloaded when needed

Or can be easily downloaded when needed 158 158 1 1 22 Kbyte 22 Kbyte 60 60 58 Kbyte 58 Kbyte Combined Combined 179 179 1 1 14 Kbyte 14 Kbyte 44 44 57 Kbyte 57 Kbyte Routing Routing 80 80 1 1 12 Kbyte 12 Kbyte 16 16 60 Kbyte 60 Kbyte Logic Logic # # Files Files File Size File Size # # Files Files Average Average File Size File Size Memory Memory Reduction Reduction Factor Factor Processor Processor Download Download Resource Resource Tested Tested

42

Summary Summary

• Growing use of FPGAs in systems and

Growing use of FPGAs in systems and SoCs SoCs

• FPGA testing is necessary but difficult due to

FPGA testing is necessary but difficult due to

• Programmability

Programmability

• Complex interconnect network

Complex interconnect network

• Logic BIST is simple compared to routing BIST

Logic BIST is simple compared to routing BIST

• Constantly growing size and changing architectures

Constantly growing size and changing architectures

• Incorporation of new and different cores

Incorporation of new and different cores

• Test development is time consuming

Test development is time consuming

• New FPGA capabilities help BIST

New FPGA capabilities help BIST

• Dynamic partial reconfiguration and

Dynamic partial reconfiguration and readback readback

• Configuration by processor cores

Configuration by processor cores