Overview of Virtex Virtex 4 4 Overview of & Virtex Virtex 4 - - PowerPoint PPT Presentation

1/18/06 VLSI Design & Test Seminar 1

Overview of Overview of Virtex Virtex 4 4 & & Virtex Virtex 4 BIST Project 4 BIST Project

1/18/06 VLSI Design & Test Seminar 2

FPGA Testing Challenges FPGA Testing Challenges

• Programmability

Programmability

• Must test all modes of operation

Must test all modes of operation

• Architectures designed for applications

Architectures designed for applications

• Testability is after thought

Testability is after thought

• Left to product/test engineers

Left to product/test engineers

• Constantly growing size

Constantly growing size

• Reconfiguration dominates test time

Reconfiguration dominates test time

• Constantly changing architectures

Constantly changing architectures

• Incorporation of new and different cores

Incorporation of new and different cores

1/18/06 VLSI Design & Test Seminar 3

Xilinx Xilinx Virtex Virtex 4 FPGAs 4 FPGAs

• Array of 1,536 to 22,272 PLBs

Array of 1,536 to 22,272 PLBs

• 4

4 LUTs/RAMs LUTs/RAMs (4 (4-

• input)

input)

• 4

4 LUTs LUTs (4 (4-

• input)

input)

• 8 FF/latches

8 FF/latches

• 48 to 552 18K

48 to 552 18K-

• bit dual

bit dual-

• port

port RAMs RAMs

• Also operate as

Also operate as FIFOs FIFOs

• Also operate as 36K

Also operate as 36K-

• bit

bit RAMs RAMs with ECC (Hamming) with ECC (Hamming)

• 32 to 512 DSP cores 48

32 to 512 DSP cores 48-

• bits

bits

• 0 to 2 PowerPC processor

0 to 2 PowerPC processor cores cores

=Xtreme DSP =PLBs =Block RAMs/FIFOs =I/O Buffers =Guard Band Area

PPC PPC

1/18/06 VLSI Design & Test Seminar 4

Virtex Virtex 4 BIST Project 4 BIST Project

• BIST for

BIST for CLBs CLBs = = Sachin Sachin Dhingra Dhingra

• BIST for I/O Buffers =

BIST for I/O Buffers = Sudheer Sudheer Vemula Vemula

• BIST for

BIST for RAMs RAMs & & DSPs DSPs = Daniel Milton = Daniel Milton

• Guard Band (w/BIST) = Lee Lerner

Guard Band (w/BIST) = Lee Lerner

• BIST for Interconnect = Chuck Stroud

BIST for Interconnect = Chuck Stroud

• Project scheduled for completion this

Project scheduled for completion this year year

1/18/06 VLSI Design & Test Seminar 5

Logic BIST for Virtex 4 Logic BIST for Virtex 4 FPGAs Using Embedded FPGAs Using Embedded Microprocessor Microprocessor

Sachin Sachin Dhingra Dhingra

VLSI Design & Test Seminar - January 2006

1/18/06 VLSI Design & Test Seminar 6

Outline Outline

• Introduction

Introduction

• Partial Configuration Readback

Partial Configuration Readback

• Comparison

Comparison

• Virtex 2 Pro

Virtex 2 Pro

• Virtex 4

Virtex 4

• Logic BIST Using Embedded Processor

Logic BIST Using Embedded Processor

• PowerPC/Microblaze

PowerPC/Microblaze

• New approach

New approach

• Circular Comparison BIST Architecture

Circular Comparison BIST Architecture

1/18/06 VLSI Design & Test Seminar 7

Introduction Introduction

• Built

Built-

• In Self Test (BIST) for FPGAs

In Self Test (BIST) for FPGAs

• Program some Programmable Logic Blocks (PLBs) as Test Pattern

Program some Programmable Logic Blocks (PLBs) as Test Pattern Generators (TPGs) and Output Response Analyzers (ORAs) to test Generators (TPGs) and Output Response Analyzers (ORAs) to test the remaining resources of the FPGA the remaining resources of the FPGA

• Diagnosis and Fault Tolerant Operation

Diagnosis and Fault Tolerant Operation

• No area overhead

No area overhead

• Issues

Issues

• Large number of Configurations => High memory requirements

Large number of Configurations => High memory requirements

• Slow Configuration Speeds => Long test times

Slow Configuration Speeds => Long test times

• Proposed Solutions

Proposed Solutions

• Partial Reconfiguration

Partial Reconfiguration

• Partial Configuration Memory Readback

Partial Configuration Memory Readback

• BIST using Embedded Processor

BIST using Embedded Processor

1/18/06 VLSI Design & Test Seminar 8

Partial Configuration Memory Readback Partial Configuration Memory Readback

• Recent FPGAs allow configuration

Recent FPGAs allow configuration memory readback of only a section memory readback of only a section

• f FPGA
• f FPGA
• Column based configuration

Column based configuration memory using frames spanning memory using frames spanning entire columns entire columns

• Only the frames containing BIST

Only the frames containing BIST results are read results are read

• Frames for FFs in ORA columns only

Frames for FFs in ORA columns only

• Time saved compared to Full

Time saved compared to Full Configuration Memory Readback Configuration Memory Readback

• Saves Logic & Routing resources

Saves Logic & Routing resources

• Scan Chain is absent

Scan Chain is absent

Empty PLB Empty PLB Block Under Test (BUT) Block Under Test (BUT) Test Pattern Generator (TPG) Test Pattern Generator (TPG) Output Response Analyzer (ORA) Output Response Analyzer (ORA) ORA Flip ORA Flip-

• Flip

Flip

1/18/06 VLSI Design & Test Seminar 9

Comparison of V2P and V4 Comparison of V2P and V4 for Logic BIST for Logic BIST

Virtex 4 Virtex 2 Pro XY CLB co XY CLB co-

• ordinates
• rdinates

Similar to V2P w/ minor changes Similar to V2P w/ minor changes Row Row-

• Column CLB co

Column CLB co-

• ordinates
• rdinates

Minor changes from Virtex I Minor changes from Virtex I XDL XDL Top and Bottom Halves Top and Bottom Halves Left and Right Halves Left and Right Halves Location of 2 Location of 2 PPCs PPCs Better Better Poor Poor Slice Testability Slice Testability 2 slices of 2 types 2 slices of 2 types SliceL (logic) & SliceM (memory) SliceL (logic) & SliceM (memory) All four Identical slices All four Identical slices PLB PLB

Virtex 4 Virtex 4 Virtex 2 Pro Virtex 2 Pro

1/18/06 VLSI Design & Test Seminar 10

BIST Using Embedded Processor BIST Using Embedded Processor

• Embedded Processor runs BIST and diagnosis

Embedded Processor runs BIST and diagnosis

• PowerPC

PowerPC

• Microblaze

Microblaze

• No dedicated resources for embedded processor

No dedicated resources for embedded processor

• FPGA resources are required for interface to

FPGA resources are required for interface to

• Program memory (block

Program memory (block RAMs RAMs) )

• Internal Configuration Access Port (ICAP)

Internal Configuration Access Port (ICAP)

• UART (hyper

UART (hyper-

• terminal interface to PC)

terminal interface to PC)

• Read

Read-

• Modify

Modify-

• Write using ICAP module

Write using ICAP module

• Fast partial reconfiguration

Fast partial reconfiguration

• Verification and debug procedure for development

Verification and debug procedure for development

• Fault injection emulation

Fault injection emulation

• FPGA is divided in two sections for testing:

FPGA is divided in two sections for testing:

• Embedded Processor

Embedded Processor

• BIST circuitry

BIST circuitry

1/18/06 VLSI Design & Test Seminar 11

Embedded Processors in V2P Embedded Processors in V2P

Microblaze - Soft Core ( Can be placed anywhere on the device ) PowerPC - Hard Core ( Fixed position in a device )

1/18/06 VLSI Design & Test Seminar 12

Comparing Embedded Processors Comparing Embedded Processors

450 MHz (max) 450 MHz (max) 200 MHz (max) 200 MHz (max) Speed Speed EDK EDK EDK EDK Compiler* Compiler* Selected Virtex 2 Pro Selected Virtex 2 Pro and Virtex 4 FX only and Virtex 4 FX only all Virtex 2, Virtex 2 all Virtex 2, Virtex 2 Pro, Pro, Virtex Virtex 4 devices 4 devices Availability Availability 36 36 40 40 BRAM count BRAM count 16 16 16 16 BRAM count** BRAM count** 820 820 900 900 Slice count** Slice count** 1035 1035 1000 1000 Slice count Slice count Fixed Fixed -

• hard core has fixed

hard core has fixed location in FPGA location in FPGA

Variable Variable –

– can be

can be located anywhere in FPGA located anywhere in FPGA

Location Location

PowerPC PowerPC Microblaze Microblaze

* Processor type is EDK compiler option - same code works for both Microblaze and PowerPC without any modifications ** Compacted Design

1/18/06 VLSI Design & Test Seminar 13

BIST Architecture BIST Architecture

Large Devices Small Devices

CUT CUT CUT CUT Embedded Embedded Processor Processor

• BIST in part of the FPGA

BIST in part of the FPGA

• Embedded Processor occupies rest

Embedded Processor occupies rest

• Hard core or

Hard core or

• Soft core (easier to move)

Soft core (easier to move)

• Embedded processor also consists

Embedded processor also consists

• f peripheral devices:
• f peripheral devices:
• UART

UART

• Memory interface

Memory interface

• BUS arbiter

BUS arbiter

• ICAP Module

ICAP Module

• BIST and processor swap places

BIST and processor swap places for next test session for next test session

Embedded Embedded Processor Processor

1/18/06 VLSI Design & Test Seminar 14

Logic BIST Architecture Logic BIST Architecture

Logic BIST Logic BIST Circuitry Circuitry Embedded Embedded Processor Processor

• Four

Four Test Sessions Test Sessions

• Right Half

Right Half – – East East

• Right Half

Right Half – – West West

• Left Half

Left Half – – East East

• Left Half

Left Half – – West West

• Two

Two Test Slice sets for V2P Test Slice sets for V2P

• Only 2 of 4 slices can be tested in

Only 2 of 4 slices can be tested in

• ne configuration
• ne configuration
• Single

Single Test Slice set for V4 Test Slice set for V4

• More testable slice architecture

More testable slice architecture

• Diagnostic Resolution

Diagnostic Resolution

• Depends on ORA design and

Depends on ORA design and connections to BUTs connections to BUTs

1/18/06 VLSI Design & Test Seminar 15

Circular Comparison Logic BIST Circular Comparison Logic BIST

• Architecture

Architecture

• TPG moved to processor portion of

TPG moved to processor portion of FPGA FPGA

• Can be performed by processor

Can be performed by processor

• ORA column instead of TPGs

ORA column instead of TPGs

• Circular comparison of BUTs

Circular comparison of BUTs

• Higher diagnostic

Higher diagnostic resolution resolution

• BUTs on the edges are now compared

BUTs on the edges are now compared by two ORAs by two ORAs

• Needs sufficient routing

Needs sufficient routing resources resources

Empty PLB Block Under Test (BUT) Test Pattern Generator (TPG) Output Response Analyzer (ORA)

1/18/06 VLSI Design & Test Seminar 16

Virtex 2 Pro (XC2VP30) Virtex 2 Pro (XC2VP30) Circular Comparison Logic BIST Circular Comparison Logic BIST

Circular Comparison BIST Circuitry TPGs (inside the processor half) Microblaze Block RAMs

1/18/06 VLSI Design & Test Seminar 17

Defining Area Constraints Defining Area Constraints

Area Constraints defined using PACE BIST Circuitry Microblaze Block RAMs

Area constraints defined using XDL

1/18/06 VLSI Design & Test Seminar 18

Virtex 4 FX12 with Logic BIST Virtex 4 FX12 with Logic BIST

6 Rows for Guard 6 Rows for Guard Band Testing Band Testing Complete FPGA Complete FPGA Half FPGA Half FPGA

1/18/06 VLSI Design & Test Seminar 19

Logic BIST for V4 Logic BIST for V4 SliceL SliceL

Fault Coverage (FC)

50 100 150 200 250 300 350 400 450 1 2 3 4 5 6 7 8 9 10 Configuration # # Faults Detected 0.0 10.0 20.0 30.0 40.0 50.0 60.0 70.0 80.0 90.0 100.0 FC (%) Individual FC Cumulative FC

1/18/06 VLSI Design & Test Seminar 20

Summary & Conclusions Summary & Conclusions

• Processor of choice: Microblaze

Processor of choice: Microblaze

• Reconfiguration

Reconfiguration

• Results retrieval

Results retrieval

• Diagnostics

Diagnostics

• Better testability of PLBs in V4 architecture

Better testability of PLBs in V4 architecture

• Higher diagnostic resolution

Higher diagnostic resolution

• Fewer Configurations

Fewer Configurations

• Circular Comparison Logic BIST possible due to

Circular Comparison Logic BIST possible due to abundance of routing resources abundance of routing resources

• Lesser details about the architecture

Lesser details about the architecture

• Increased development time

Increased development time

1/18/06 VLSI Design & Test Seminar 21

Built Built-

• In Self

In Self-

• Test for

Test for Programmable I/O Buffers Programmable I/O Buffers in in FPGAs FPGAs and and SoCs SoCs

Sudheer Vemula Sudheer Vemula

1/18/06 VLSI Design & Test Seminar 22

Motivation Motivation

• FPGAs

FPGAs consist of consist of

• Programmable Logic Blocks

Programmable Logic Blocks ( (PLBs PLBs) )

• Routing Resources

Routing Resources

• Interconnect points

Interconnect points

• I/O Buffers

I/O Buffers

• BIST configurations have been

BIST configurations have been developed to test logic and developed to test logic and routing resources in the core of routing resources in the core of an FPGA. an FPGA.

• BIST configurations were not

BIST configurations were not developed to test the I/O developed to test the I/O (Input/Output) buffers in an (Input/Output) buffers in an FPGA. FPGA.

1/18/06 VLSI Design & Test Seminar 23

Types of I/O Buffers Types of I/O Buffers

• Every I/O Buffer can be:

Every I/O Buffer can be:

• Input

Input

• Output

Output

• Bi

Bi-

• directional

directional

• Connections

Connections

• Bonded I/O

Bonded I/O

• Unbonded

Unbonded I/O I/O

• Types (in some FPGAs)

Types (in some FPGAs)

• Primary I/O Buffer

Primary I/O Buffer

• Secondary I/O Buffer

Secondary I/O Buffer

• Clock Buffer

Clock Buffer

PLB PLB I/O I/O I/O I/O I/O

= primary I/O buffer = secondary I/O buffer

X X X X X X X X Y Y Y Y Y Y Y Y TC OUT IN PAD

to/from internal programmable routing resources

1/18/06 VLSI Design & Test Seminar 24

Architecture of Atmel I/O Buffer Architecture of Atmel I/O Buffer

Routing associated with the I/O Buffer

1/18/06 VLSI Design & Test Seminar 25

Resources in I/O Buffer Resources in I/O Buffer

• I/O buffers have several programmable features

I/O buffers have several programmable features

• Multiplexers

Multiplexers

• Flip

Flip-

• flops or Latches

flops or Latches

• Pull

Pull-

• up, Pull

up, Pull-

• down capabilities

down capabilities

• Delays, Slew rate, I/O Standards

Delays, Slew rate, I/O Standards

• Drive capabilities, Tri

Drive capabilities, Tri-

• state enable

state enable

• Transmission Gates

Transmission Gates

• Global Reset Connection

Global Reset Connection

1/18/06 VLSI Design & Test Seminar 26

Basic Testing Approach Basic Testing Approach

from TPG to ORA

1/18/06 VLSI Design & Test Seminar 27

General I/O Buffer BIST Architecture General I/O Buffer BIST Architecture

• TPG may be a counter or an LFSR

TPG may be a counter or an LFSR

• ORA is comparison

ORA is comparison-

• based to latch mismatches due to

based to latch mismatches due to faults faults

• Output of each I/O buffer is compared by two

Output of each I/O buffer is compared by two ORAs ORAs with the outputs of two other buffers with the outputs of two other buffers

• Circular comparison improves diagnostic resolution

Circular comparison improves diagnostic resolution

=TPG =ORA

1/18/06 VLSI Design & Test Seminar 28

Manufacturing vs. In Manufacturing vs. In-

• System Test

System Test

• In Manufacturing test all the bonded and

In Manufacturing test all the bonded and unbonded unbonded IOBs IOBs can be tested can be tested

• Independent of package

Independent of package

• Routing associated with the

Routing associated with the IOBs IOBs can also be can also be tested tested

• In system level testing only the output

In system level testing only the output buffers are tested buffers are tested

• Testing the input buffers will back drive them

Testing the input buffers will back drive them

1/18/06 VLSI Design & Test Seminar 29

Atmel Implementation Atmel Implementation

• 3 BIST configurations developed using MGL

3 BIST configurations developed using MGL

• Configurations test

Configurations test

• primary I/O

primary I/O

• secondary I/O

secondary I/O

• global reset in primary and secondary I/O

global reset in primary and secondary I/O

• Subsequent BIST configurations via dynamic partial

Subsequent BIST configurations via dynamic partial reconfiguration from AVR reconfiguration from AVR

• 12 for primary I/O

12 for primary I/O

• 9 for secondary I/O

9 for secondary I/O

• Approximately 2x3

Approximately 2x3N N for global reset for global reset

• N

N = # = # PLBs PLBs in one dimension of in one dimension of N Nx xN N array array

• N=24 for AT94K10

N=24 for AT94K10

• N=48 for AT94K40

N=48 for AT94K40

• AVR dynamic partial reconfiguration reduces test time

AVR dynamic partial reconfiguration reduces test time

• Particularly when testing global reset

Particularly when testing global reset

1/18/06 VLSI Design & Test Seminar 30

Fault Simulation Results for AT94K Fault Simulation Results for AT94K

100% fault coverage is obtained with additional configuration fo 100% fault coverage is obtained with additional configuration for global reset r global reset

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 2 3 4 5 6 7 8 9 10 11 12 13

BIST Configurations Fault Coverage (FC)

1/18/06 VLSI Design & Test Seminar 31

Atmel Summary Atmel Summary

• Number of BIST configurations for I/O buffers is high

Number of BIST configurations for I/O buffers is high

• Compared to 16 for logic BIST and 48 for routing BIST

Compared to 16 for logic BIST and 48 for routing BIST

• Can achieve 100% gate level stuck

Can achieve 100% gate level stuck-

• at fault coverage

at fault coverage

• Major defects in analog circuitry of IOB are detected in both th

Major defects in analog circuitry of IOB are detected in both the e approaches approaches

• Parametric faults like V

Parametric faults like VOL

OL, V

, VOH

OH, delay defects, current sink and source

, delay defects, current sink and source capabilities may not be detected capabilities may not be detected A V R I/O buffers north comparison loop east comparison loop west comparison loop south comparison loop

1/18/06 VLSI Design & Test Seminar 32

I/O Buffers in I/O Buffers in Virtex Virtex 4 4

• Every I/O Buffer consists

Every I/O Buffer consists

• ILOGIC (Input Logic)

ILOGIC (Input Logic)

• OLOGIC (Output Logic)

OLOGIC (Output Logic)

• PAD

PAD

• IOBs

IOBs are paired to be able are paired to be able to operate as a differential to operate as a differential pair pair

• Each can be accessed

Each can be accessed individually in Single Data individually in Single Data Rate (SDR) mode Rate (SDR) mode

I/O Blocks in the FPGA Editor

1/18/06 VLSI Design & Test Seminar 33

ILOGIC Block ILOGIC Block

• Gets input from the pad

Gets input from the pad

• Consists of

Consists of

• 64 tap delay element

64 tap delay element (variable or fixed) (variable or fixed)

• Flip

Flip-

• Flops (registered outputs

Flops (registered outputs and Double Data Rate (DDR) and Double Data Rate (DDR) registers) registers)

• 3 different outputs

3 different outputs

• Unregistered direct

Unregistered direct connection connection

• Different modes of operation

Different modes of operation

• f DDR registers
• f DDR registers
• Only upper register can be

Only upper register can be configured as either Flip configured as either Flip-

• Flop or latch

Flop or latch

ILOGIC Block in ILOGIC Block in the FPGA Editor the FPGA Editor

1/18/06 VLSI Design & Test Seminar 34

IDDR Modes and ISERDES IDDR Modes and ISERDES

• IDDR registers can be operated in 3 modes

IDDR registers can be operated in 3 modes

• Opposite Edge Mode (2 registers)

Opposite Edge Mode (2 registers)

• Same Edge Mode (3 registers)

Same Edge Mode (3 registers)

• Same Edge Pipelined mode (4 registers)

Same Edge Pipelined mode (4 registers)

• ILOGIC block can also be operated in input

ILOGIC block can also be operated in input serial serial-

• to

to-

• parallel mode

parallel mode

• ISERDES can be operated in either Single Data

ISERDES can be operated in either Single Data Rate (SDR) or DDR mode Rate (SDR) or DDR mode

• SDR Mode

SDR Mode – – Creates 2 Creates 2-

• 8 bit parallel word

8 bit parallel word

• DDR Mode

DDR Mode – – Creates 4, 6, 8, or 10 Creates 4, 6, 8, or 10-

• bit parallel word

bit parallel word

1/18/06 VLSI Design & Test Seminar 35

OLOGIC Block OLOGIC Block

• Sources output to the

Sources output to the pad pad

• 6 storage elements

6 storage elements

• 3 for tri

3 for tri-

• state control

state control

• 3 for output data

3 for output data

• Both sets of registers

Both sets of registers have same have same functionality functionality

• Only upper register

Only upper register can be configured as can be configured as either Flip either Flip-

• Flop or

Flop or latch latch

OLOGIC Block in OLOGIC Block in the FPGA Editor the FPGA Editor

1/18/06 VLSI Design & Test Seminar 36

ODDR Modes and OSERDES ODDR Modes and OSERDES

• ODDR registers operate in 3 modes

ODDR registers operate in 3 modes

• Opposite Edge Mode (2 registers)

Opposite Edge Mode (2 registers)

• Same Edge Mode (3 registers )

Same Edge Mode (3 registers )

• OLOGIC block can be operated in output

OLOGIC block can be operated in output parallel to serial converter mode parallel to serial converter mode

• OSERDES can be operated in either

OSERDES can be operated in either Single Data Rate (SDR) or DDR mode Single Data Rate (SDR) or DDR mode

• SDR Mode

SDR Mode – – Converts 2 Converts 2-

• 8 bit parallel word to

8 bit parallel word to serial serial

• DDR Mode

DDR Mode – – Converts 4, 6, 8 or 10 Converts 4, 6, 8 or 10-

• bit

bit parallel word to serial parallel word to serial

1/18/06 VLSI Design & Test Seminar 37

Summary Summary

• A BIST approach to test the programmable

A BIST approach to test the programmable IOBs IOBs

• f any FPGA or FPGA core in an
• f any FPGA or FPGA core in an SoC

SoC

• Implementation results for the Atmel

Implementation results for the Atmel IOBs IOBs

• Architecture of the

Architecture of the IOBs IOBs in Xilinx Virtex in Xilinx Virtex-

• 4

4 FPGAs FPGAs

• BIST configurations are being developed for Virtex

BIST configurations are being developed for Virtex-

• 4

4

• Publications

Publications

• Vemula

Vemula & Stroud, & Stroud, “ “BIST of I/O Buffers in Atmel BIST of I/O Buffers in Atmel FPGAs FPGAs ” ”, IEEE North Atlantic Test Workshop, 2005 , IEEE North Atlantic Test Workshop, 2005

• Vemula

Vemula & Stroud, & Stroud, “ “BIST for Programmable I/O BIST for Programmable I/O Buffers in Buffers in FPGAs FPGAs and and SoCs SoCs ” ”, IEEE Southeastern , IEEE Southeastern Symp

• Symp. on System Theory, 2006

. on System Theory, 2006