HCAL Back End Requirements and Architecture A. Belloni University - - PowerPoint PPT Presentation

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HCAL Back End Requirements and Architecture A. Belloni University - - PowerPoint PPT Presentation

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HCAL Back End Requirements and Architecture A. Belloni University of Maryland Biographical Notes Assistant Professor, University of Maryland 2007 Ph.D. Massachusetts Institute of Technology Relevant positions 2014-present:

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SLIDE 1

HCAL Back End Requirements and Architecture

  • A. Belloni – University of Maryland
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SLIDE 2
  • Assistant Professor, University of Maryland
  • 2007 Ph.D. – Massachusetts Institute of Technology
  • Relevant positions
  • 2014-present: US CMS L4 manager, Phase-I Upgrade:

HB/HE/HF ngCCM

  • 2015-present: HCAL Test Beam Run Coordinator
  • 2016-present: US CMS L3 manager, Phase-II Upgrade: HCAL

Barrel

  • Former experience: ATLAS Muon MDT chambers, DAQ,

installation, commissioning

2

Biographical Notes

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 3
  • Requirements for HL-LHC
  • Current configuration of Hadronic Barrel Back-end

Electronics (HB BE)

  • Almost current: expected configuration at end of Phase-I

Upgrade

  • Proposed configuration for HB BE during HL-LHC
  • Including interfaces with front-end and DAQ
  • HCAL-specific test path

Outline

8/29/2017

  • A. Belloni :: HCAL BE

3

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SLIDE 4

4

HB BE Electronics Upgrade Overview

  • A. Belloni :: HCAL BE

8/29/2017

Key reason for upgrade 5.0Gbps data links 2.4Gbps Clock Control Powerful FPGA Feature extraction, Trigger primitive formation L1 Trigger DAQ Sustain L1 trigger rate up to 750kHz TCDS++ HB RBX

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SLIDE 5
  • Design guidelines
  • uTCA-based system: widely used in CMS, easy to maintain,

economical, compact

  • FE has no buffers for data, BE does processing for trigger and

DAQ: flexible system – algorithms run in low-radiation environment

5

Legacy HB BE Configuration

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 6
  • uHTR
  • Receives data from front-end to

prepare them for trigger, luminosity, data acquisition system

  • AMC13
  • First and customized crate

management and data hub unit

  • Used also in trigger system and in

clock/timing system

  • Sends data from crate to DAQ
  • Commercial parts
  • uTCA crates
  • MCH
  • Second crate management and

data hub

  • Power modules and AC/DC

converters

6

Legacy BE Key components

  • A. Belloni :: HCAL BE

8/29/2017

uHTR AMC13 MCH Power

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SLIDE 7
  • Functions
  • Store data and transfer to DAQ via AMC13 on trigger
  • Produce trigger primitives
  • Luminosity info to CMS and LHC LumiDAQ (HF only)
  • Key design features
  • FPGA provides flexibility; firmware in source control system
  • Modular design with mezzanines (power, control…) makes QA and

maintenance easier

7

Legacy uHTR Design Notes

  • A. Belloni :: HCAL BE

8/29/2017

Lessons for design of Phase-II BE

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SLIDE 8
  • No upgrades foreseen for FE
  • Legacy system organized in 36 readout boxes (RBX), each of

which controls and reads out a 20-degree f wedge in one hemisphere

  • Total number of readout channels per RBX: 252
  • Clock and control via ngCCM board
  • One board per RBX

8

Phase-II FE Overview

  • A. Belloni :: HCAL BE

8/29/2017

Replaced by BCP in ATCA crate

FEE Card (16 channels)

FEE Module (64 channels)

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SLIDE 9
  • Data path
  • No changes with respect to legacy system; same transverse and

longitudinal segmentation, same number of channels

  • 15 h towers with 4 longitudinal depths and 1 h tower with 3 depths in

each 5-degree f wedge: 252 channels per RBX; 9072 channels for whole HB

  • Data rate: 5Gbps
  • Clock and control path
  • Four ngCCM with two bi-directional links per RBX
  • Catastrophic failure of ngCCM board loses 1/4-RBX (~0.7% of HB)
  • Link rate: 2.4Gbps
  • Trigger path
  • Trigger primitives will remain similar to Phase-I primitives
  • 2304 trigger towers, each sending 16-bit trigger primitive
  • 10 bits: energy sum of entire trigger tower (all longitudinal depths) plus

6 feature bits

  • Algorithms to define the feature bits are being designed

9

Phase-II FE Summary

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 10
  • BE needs to sustain trigger rate of 750kHz, and

latency of 12.5ms, required by HL-LHC trigger system

  • uHTR does not have sufficient bandwidth, and will be replaced by

board in ATCA standard

  • HB will use the same BCP board being designed for

EB BE

  • Value engineering example: “[using the same board] optimizes

the usage of development and production resources, enables the sharing of spares, achieves homogeneity in the trigger primitive generation, and facilitates long-term operations and maintenance” (from the Phase-II HCAL TDR)

  • Firmware will be adapted to work in HB environment

10

Phase-II BE Design and Requirements

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 11
  • EB and HB use common ATCA platform
  • 16Gbps optical links to DAQ and Trigger

11

Phase-II HB Electronics Schema

  • A. Belloni :: HCAL BE

8/29/2017

16 channels

QIE11

1 RBX (4 RMs cards or 16 QIE cards )

256 channels 32 optical links @ 5.0 Gb/s

x 16 2 links Versatile

QIE cards

  • Two UltraScale FPGA -

ATCA blade Trigger, DAQ, FE control

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SLIDE 12
  • Readout unit is 20-degree f wedge in
  • ne hemisphere
  • Corresponds to one RBX
  • Contains 16x4 h-f trigger towers
  • 0<|h|<1.392
  • Each region is served by one FPGA in

an ATCA blade

  • Two FPGAs per blade
  • HB BE needs a total of 36 FPGAs

12

Readout Schema

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 13

13

BE-to-FE Interface

  • A. Belloni :: HCAL BE

8/29/2017

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4

Tower

Tower

20-degree wedge

+ η

  • φ

Total number of HB Back-End FPGAs 36

16 η segments x 2@5.0Gb/s + 4 bi-directional @2.4Gb/s = 40 links (32+4 upstream & 4 downstream)

One FPGA 64 Towers Total number of FE to BE links: 1440 Number of links Per BE FPGA is 40

4 up + 4 down

Control /Status

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SLIDE 14

14

BE-to-Trigger Interface

  • A. Belloni :: HCAL BE

8/29/2017

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 3 4

Tower

Tower

20-degree wedge

+ η

  • φ

Total number of HB Back-End FPGAs 36 One FPGA 64 Towers Total number of BE to L1T links: 228 Number of links per BE card is 8

16Gb/s link

  • Assuming TPs with 16 bits x 4 depths
  • Each optical link includes TPs from 2 η (8 towers)

8 links x 16Gb/s

16Gb/s link

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SLIDE 15
  • Inputs
  • 5.0Gbps (8b10b) upstream payload: 88 bits
  • 2x88 bits per 4 towers: 176 bits
  • 16 h towers: 2816 bits
  • Input readout size (assume 10 BXs): 28160 bits
  • Outputs
  • 64 trigger towers x 64 bits (trigger primitive size with 4 oversampling): 4096
  • Output readout size, assuming 10 BX: 40960 bits
  • Readout window
  • 28160 + 40960 = 69120 bits (event size ~ 8.5KB)
  • DAQ payload at 750kHz trigger rate
  • 69120 bits x 750kHz = 52Gbps
  • 4 x 16Gbps per FPGA needed to send event to DAQ
  • Total number of DAQ links: 144

15

BE-to-DAQ Interface

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 16
  • Based on FPGA UltraScale package: B2104
  • 46 transceivers needed
  • 36 inputs
  • 32 @ 5.0Gbps: upstream links from FE (QIE cards)
  • 4 @ 2.4Gbps: status links from RBX (ngCCM)
  • 16 outputs
  • 8 @ 16Gbps: trigger primitives
  • 4 @ 2.4Gbps: control links to RBX (ngCCM)
  • 4 @ 16Gbps: DAQ
  • 2 control links
  • TTC, TTS, DAQ flow control

16

The BCP board (ATCA blade format)

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 17
  • Build readout chain with HB FE and CTP7 board in

uTCA crate

  • Plan to follow schedule of EB electronics demo
  • Replace CTP7 with ATCA blade
  • First test of complete Phase-II readout chain
  • Perform slice test at CERN TB
  • Full chain, including actual scintillators and photosensors
  • HB-specific: firmware
  • Plan to use same back-end hardware as EB; need to develop

firmware to talk to HB front-end

17

HB-Specific Test Path

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 18

18

Test of Readout Chain

  • A. Belloni :: HCAL BE

8/29/2017

32 GBT links (QIE data) 1 GBT link (control, bc0, clock) Host PC bc 0 LHC clock C T P 7

A M C 1 3 M C H

μTCA Crate spy QIE data HB RBX

  • EB demo exists in CERN Lab
  • May need HB adapter boards between FE

and CTP7

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SLIDE 19
  • A 20-degree HB wedge is installed along the

H2 beam line

  • CMS HCAL maintains a control room with a complete

slice of the DAQ and clock-and-control systems

  • Plan to install an ATCA crate, with two BCP

blades, to test their performance and firmware

  • Asynchronous beam; pions, electrons, muons in the

20-300GeV range

19

Slice Test

  • A. Belloni :: HCAL BE

8/29/2017

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SLIDE 20
  • Required upgrade to satisfy HL-LHC data taking

conditions

  • HB BE foreseen to use the same hardware as EB BE
  • Improve usage of production and development resources, facilitate

long-term operations and maintenance

  • Project costs and deliverables scale with number of

channel in EB vs HB

  • 216 BCP for EB vs 36 for HB
  • Reserve resources to work on HB-specific firmware
  • Quality assurance follows recommended guidelines
  • Foresee production of prototype and pre-production boards, with

resources allocated to promptly implement design updates

  • CTP7, then ATCA demonstrator setup
  • Slice test at CERN test beam

20

Summary

  • A. Belloni :: HCAL BE

8/29/2017