SMD150 Computer Architecture Andrey Kruglyak Note: some of todays - - PowerPoint PPT Presentation

▶
smd150 computer architecture
SMART_READER_LITE
LIVE PREVIEW

SMD150 Computer Architecture Andrey Kruglyak Note: some of todays - - PowerPoint PPT Presentation

Oct 11, 2023 182 likes •523 views

SMD150 Computer Architecture Andrey Kruglyak Note: some of todays slides are by Jonas Thor Today Introduction to VHDL - VHSIC Hardware Description Language crash course with examples SyncSim, new version how to create

slide-1
SLIDE 1

SMD150 Computer Architecture

Andrey Kruglyak

Note: some of today’s slides are by Jonas Thor

slide-2
SLIDE 2

SMD150 Computer Architecture Andrey Kruglyak, 2007

Today

  • Introduction to

VHDL - VHSIC Hardware Description Language

  • crash course with examples
  • SyncSim, new version
  • how to create

VHDL components in SyncSim

  • how to connect components in SyncSim
  • MIPS memory component (if we have time)
slide-3
SLIDE 3

SMD150 Computer Architecture Andrey Kruglyak, 2007

Logic Gates

slide-4
SLIDE 4

SMD150 Computer Architecture Andrey Kruglyak, 2007

Introduction to VHDL

  • Hardware Description Language
  • Current standard is IEEE 1076-1993 (VHDL-93)
  • ADA-like syntax, strictly typed language
  • Can be used for modeling, simulating (with a variety of tools), and

automatically synthesize digital circuits

  • Important properties:
  • can express concurrency (changes occurring in parallel)...
  • ...but also allows sequential execution of statements
  • allows to structure a design hierarchically
slide-5
SLIDE 5

SMD150 Computer Architecture Andrey Kruglyak, 2007

VHDL Design Units

  • Entity = a component, a part of the circuit with defined interface and

functionality

  • entity declaration specifies input and output ports
  • architecture of an entity specifies the function of the entity
  • An entity can contain other entities as its integral parts
slide-6
SLIDE 6

SMD150 Computer Architecture Andrey Kruglyak, 2007

Entity Declaration

entity Adder is port (A, B : in std_logic_vector(3 downto 0); CarryIn : in std_logic; Sum : out std_logic_vector(3 downto 0); CarryOut : out std_logic); end Adder;

  • an input must have a driver or be a constant
  • an output may be left open (not in SyncSim)
slide-7
SLIDE 7

SMD150 Computer Architecture Andrey Kruglyak, 2007

Entity Architecture

entity Adder is port (A, B : in std_logic_vector(3 downto 0); CarryIn : in std_logic; Sum : out std_logic_vector(3 downto 0); CarryOut : out std_logic); end Adder; architecture Demo of Adder is

  • - component declarations
  • - type, signal, and variable declarations

begin

  • - concurrent statements (+ sequential statements within processes)

end Demo;

slide-8
SLIDE 8

SMD150 Computer Architecture Andrey Kruglyak, 2007

Other VHDL Definitions

  • You can define own types, functions, and procedures in a package
  • A number of packages form a library (such as IEEE)
  • Your own packages will belong to the default library called work
slide-9
SLIDE 9

SMD150 Computer Architecture Andrey Kruglyak, 2007

Signals, Variables, and Constants

  • Signals are concurrent objects
  • nly declared in the declarative region of an architecture

signal x : std_logic;

  • assignment does not have an immediate effect

x <= ‘0’;

  • Variables are sequential objects
  • usually declared in the declarative region of a process

variable y : std_logic;

  • assignment has an immediate effect

y := ‘1’;

  • Constant are assigned values when declared:

constant A : integer := 12;

slide-10
SLIDE 10

SMD150 Computer Architecture Andrey Kruglyak, 2007

Common Signal & Variable Types

  • bit (we will use std_logic)
  • bit_vector (we will use std_logic_vector)
  • integer
  • usually 32-bit
  • can be constrained (this maps to 8 bits):

signal byte : integer range 0 to 255;

  • boolean true, false
  • maps to 1 bit
slide-11
SLIDE 11

SMD150 Computer Architecture Andrey Kruglyak, 2007

Defining New Types

  • Enumeration types for state machines:

type state is (Idle, Enabled, Stopped); signal s : state;

  • Array types:

type my_vector is array (10 downto 0) of std_logic;

  • elements indexed from 0 (from right to left)
  • least significant bit at position 0 (right-most in binary notation, e.g.

“011101” has the least significant bit “1”)

slide-12
SLIDE 12

SMD150 Computer Architecture Andrey Kruglyak, 2007

Assigning Values

  • To one-bit signals:

A <= ‘1’;

  • To arrays:

A_vec <= “10100”; A_vec <= (‘1’, ‘0’, ‘1’, ‘0’, ‘0’); A_vec <= (4 => ‘1’, 2 => ‘1’, others => ‘0’); A_vec <= (4 | 2 => ‘1’, others => ‘0’); A_vec <= B”10100”; A_vec <= X”14”;

slide-13
SLIDE 13

SMD150 Computer Architecture Andrey Kruglyak, 2007

Array Access and Assignment

  • We can access a slice of an array or an individual element (bit)
  • We can assign a value to a slice of an array or an individual element
  • Example:

B(7 downto 5) <= A(4 downto 2); B(4 downto 0) <= ‘0’ & ‘1’ & A(2) & A(1) & A(0);

A B

7 4 1

slide-14
SLIDE 14

SMD150 Computer Architecture Andrey Kruglyak, 2007

Aliases

  • Another name for a part of a signal
  • Can be used to make code clearer
  • Example:

signal MIPS_Instruction : std_logic_vector(31 downto 0); alias Opcode : std_logic_vector(5 downto 0) is MIPS_Instruction(31 downto 26); alias RS : std_logic_vector(4 downto 0) is MIPS_Instruction(25 downto 21); alias RT : std_logic_vector(4 downto 0) is MIPS_Instruction(20 downto 16); alias RD : std_logic_vector(4 downto 0) is MIPS_Instruction(15 downto 11);

slide-15
SLIDE 15

SMD150 Computer Architecture Andrey Kruglyak, 2007

std_logic = resolved std_ulogic

  • Defined in IEEE package std_logic_1164
  • to use, place the following two lines at the beginning of a file:

library IEEE; use ieee.std_logic_1164.all;

slide-16
SLIDE 16

SMD150 Computer Architecture Andrey Kruglyak, 2007

Concurrent and Sequential VHDL

slide-17
SLIDE 17

SMD150 Computer Architecture Andrey Kruglyak, 2007

Concurrent Statements

slide-18
SLIDE 18

SMD150 Computer Architecture Andrey Kruglyak, 2007

All outputs must be set, unless we need a memory element!

Process

slide-19
SLIDE 19

SMD150 Computer Architecture Andrey Kruglyak, 2007

Process is a Concurrent Statement

slide-20
SLIDE 20

SMD150 Computer Architecture Andrey Kruglyak, 2007

Multiple Processes Interact Concurrently

slide-21
SLIDE 21

SMD150 Computer Architecture Andrey Kruglyak, 2007

In a process, you must use variables (not signals) for intermediate calculations !

Concurrent vs. Sequential Execution

slide-22
SLIDE 22

SMD150 Computer Architecture Andrey Kruglyak, 2007

Internal Signals

slide-23
SLIDE 23

SMD150 Computer Architecture Andrey Kruglyak, 2007

Variables in Processes

slide-24
SLIDE 24

SMD150 Computer Architecture Andrey Kruglyak, 2007

Some Common Concurrent and Sequential Statements

slide-25
SLIDE 25

SMD150 Computer Architecture Andrey Kruglyak, 2007

If Statement - Sequential

slide-26
SLIDE 26

SMD150 Computer Architecture Andrey Kruglyak, 2007

Case Statement - Sequential

slide-27
SLIDE 27

SMD150 Computer Architecture Andrey Kruglyak, 2007

Case Statement - Sequential

slide-28
SLIDE 28

SMD150 Computer Architecture Andrey Kruglyak, 2007

When Statement - Concurrent

slide-29
SLIDE 29

SMD150 Computer Architecture Andrey Kruglyak, 2007

With Statement - Concurrent

slide-30
SLIDE 30

SMD150 Computer Architecture Andrey Kruglyak, 2007

Writing a Synchronous Component

  • A synchronous component with asynchronous Reset

architecture synchronous of MyComponent is type state is (S0, S1, S2); signal S : state; begin process (Clk, Reset) begin if (Reset) then

  • - resetting the state

S <= S0; elsif rising_edge(Clk) then

  • - update the state from inputs
  • - calculate outputs

end if; end process; end;

slide-31
SLIDE 31

SMD150 Computer Architecture Andrey Kruglyak, 2007

Combinatorial Component

  • A combinatorial component (no reset)

architecture combinatorial of MyComponent is begin

  • - calculate outputs (no state)

end;

slide-32
SLIDE 32

Questions?