SMD150 Computer Architecture Andrey Kruglyak Note: some of todays - PowerPoint PPT Presentation

SMD150 Computer Architecture Andrey Kruglyak Note: some of today’s slides are by Jonas Thor

Today • Introduction to VHDL - VHSIC Hardware Description Language • crash course with examples • SyncSim, new version • how to create VHDL components in SyncSim • how to connect components in SyncSim • MIPS memory component (if we have time) Andrey Kruglyak, 2007 SMD150 Computer Architecture

Logic Gates Andrey Kruglyak, 2007 SMD150 Computer Architecture

Introduction to VHDL • Hardware Description Language • Current standard is IEEE 1076-1993 (VHDL-93) • ADA-like syntax, strictly typed language • Can be used for modeling, simulating (with a variety of tools), and automatically synthesize digital circuits • Important properties: • can express concurrency (changes occurring in parallel)... • ...but also allows sequential execution of statements • allows to structure a design hierarchically Andrey Kruglyak, 2007 SMD150 Computer Architecture

VHDL Design Units • Entity = a component, a part of the circuit with defined interface and functionality • entity declaration specifies input and output ports • architecture of an entity specifies the function of the entity • An entity can contain other entities as its integral parts Andrey Kruglyak, 2007 SMD150 Computer Architecture

Entity Declaration entity Adder is port (A, B : in std_logic_vector(3 downto 0); CarryIn : in std_logic; Sum : out std_logic_vector(3 downto 0); CarryOut : out std_logic); end Adder; • an input must have a driver or be a constant • an output may be left open (not in SyncSim) Andrey Kruglyak, 2007 SMD150 Computer Architecture

Entity Architecture entity Adder is port (A, B : in std_logic_vector(3 downto 0); CarryIn : in std_logic; Sum : out std_logic_vector(3 downto 0); CarryOut : out std_logic); end Adder; architecture Demo of Adder is - - component declarations - - type, signal, and variable declarations begin - - concurrent statements (+ sequential statements within processes) end Demo; Andrey Kruglyak, 2007 SMD150 Computer Architecture

Other VHDL Definitions • You can define own types, functions, and procedures in a package • A number of packages form a library (such as IEEE) • Your own packages will belong to the default library called work Andrey Kruglyak, 2007 SMD150 Computer Architecture

Signals, Variables, and Constants • Signals are concurrent objects • only declared in the declarative region of an architecture signal x : std_logic; • assignment does not have an immediate effect x <= ‘0’; • Variables are sequential objects • usually declared in the declarative region of a process variable y : std_logic; • assignment has an immediate effect y := ‘1’; • Constant are assigned values when declared: constant A : integer := 12; Andrey Kruglyak, 2007 SMD150 Computer Architecture

Common Signal & Variable Types • bit (we will use std_logic ) • bit_vector (we will use std_logic_vector ) • integer • usually 32-bit • can be constrained (this maps to 8 bits): signal byte : integer range 0 to 255; • boolean true, false • maps to 1 bit Andrey Kruglyak, 2007 SMD150 Computer Architecture

Defining New Types • Enumeration types for state machines: type state is (Idle, Enabled, Stopped); signal s : state; • Array types: type my_vector is array (10 downto 0) of std_logic; • elements indexed from 0 (from right to left) • least significant bit at position 0 (right-most in binary notation, e.g. “011101” has the least significant bit “1”) Andrey Kruglyak, 2007 SMD150 Computer Architecture

Assigning Values • To one-bit signals: A <= ‘1’; • To arrays: A_vec <= “10100”; A_vec <= (‘1’, ‘0’, ‘1’, ‘0’, ‘0’); A_vec <= (4 => ‘1’, 2 => ‘1’, others => ‘0’); A_vec <= (4 | 2 => ‘1’, others => ‘0’); A_vec <= B”10100”; A_vec <= X”14”; Andrey Kruglyak, 2007 SMD150 Computer Architecture

Array Access and Assignment • We can access a slice of an array or an individual element (bit) • We can assign a value to a slice of an array or an individual element • Example: B(7 downto 5) <= A(4 downto 2); B(4 downto 0) <= ‘0’ & ‘1’ & A(2) & A(1) & A(0); 4 7 0 1 B A 0 0 Andrey Kruglyak, 2007 SMD150 Computer Architecture

Aliases • Another name for a part of a signal • Can be used to make code clearer • Example: signal MIPS_Instruction : std_logic_vector(31 downto 0); alias Opcode : std_logic_vector(5 downto 0) is MIPS_Instruction(31 downto 26); alias RS : std_logic_vector(4 downto 0) is MIPS_Instruction(25 downto 21); alias RT : std_logic_vector(4 downto 0) is MIPS_Instruction(20 downto 16); alias RD : std_logic_vector(4 downto 0) is MIPS_Instruction(15 downto 11); Andrey Kruglyak, 2007 SMD150 Computer Architecture

std_logic = resolved std_ulogic • Defined in IEEE package std_logic_1164 • to use, place the following two lines at the beginning of a file: library IEEE; use ieee.std_logic_1164.all; Andrey Kruglyak, 2007 SMD150 Computer Architecture

Concurrent and Sequential VHDL Andrey Kruglyak, 2007 SMD150 Computer Architecture

Concurrent Statements Andrey Kruglyak, 2007 SMD150 Computer Architecture

Process All outputs must be set, unless we need a memory element! Andrey Kruglyak, 2007 SMD150 Computer Architecture

Process is a Concurrent Statement Andrey Kruglyak, 2007 SMD150 Computer Architecture

Multiple Processes Interact Concurrently Andrey Kruglyak, 2007 SMD150 Computer Architecture

Concurrent vs. Sequential Execution In a process, you must use variables (not signals) for intermediate calculations ! Andrey Kruglyak, 2007 SMD150 Computer Architecture

Internal Signals Andrey Kruglyak, 2007 SMD150 Computer Architecture

Variables in Processes Andrey Kruglyak, 2007 SMD150 Computer Architecture

Some Common Concurrent and Sequential Statements Andrey Kruglyak, 2007 SMD150 Computer Architecture

If Statement - Sequential Andrey Kruglyak, 2007 SMD150 Computer Architecture

Case Statement - Sequential Andrey Kruglyak, 2007 SMD150 Computer Architecture

Case Statement - Sequential Andrey Kruglyak, 2007 SMD150 Computer Architecture

When Statement - Concurrent Andrey Kruglyak, 2007 SMD150 Computer Architecture

With Statement - Concurrent Andrey Kruglyak, 2007 SMD150 Computer Architecture

Writing a Synchronous Component • A synchronous component with asynchronous Reset architecture synchronous of MyComponent is type state is (S0, S1, S2); signal S : state; begin process (Clk, Reset) begin if (Reset) then -- resetting the state S <= S0; elsif rising_edge(Clk) then -- update the state from inputs -- calculate outputs end if ; end process ; end ; Andrey Kruglyak, 2007 SMD150 Computer Architecture

Combinatorial Component • A combinatorial component (no reset) architecture combinatorial of MyComponent is begin -- calculate outputs (no state) end ; Andrey Kruglyak, 2007 SMD150 Computer Architecture

Questions?