ECEU530 Schedule ECE U530 Homework 6 due Wednesday, November 15 - - PDF document

SLIDE 1

ECEU530

ECE U530 Digital Hardware Synthesis

• Lecture 17:
• Homework 6: Calculator
• Memory: RAMs and ROMs (Mano and Kime Chapter 9)
• Describing Memory in VHDL
• Memories and FPGAs
• Tri-state buffers and busses
• Student project presentations:

Wednesday, Nov 15 and Monday, November 20

ECE U530 F06

lect17.ppt

• Prof. Miriam Leeser

mel@coe.neu.edu November 13, 2006

ECE U530 F’06 2

lect17.ppt

Schedule

• Homework 6 due Wednesday, November 15
• Complete the Calculator from ECEU323 in VHDL

–Write a controller –Combine controller and datapath –Use the posted entities

• Quiz 2 on December 4th
• Project Presentations:
• Wednesday November 15:

–Corey, Rishi, Oshin, John, Daryl, Natalie

• Monday, November 20:

–Shuba, Paul, Doug, Shao-Han, Samir

ECE U530 F’06 3

lect17.ppt

Rest of Semester

• Sign up to demo your working project code to me

November 20th or 21st

• Upcoming lectures:
• Tri-state buffers and busses
• Designing a complex multiply accumulator:

–Chapter 6 of Ashenden

• Quiz in class on December 4
• Project due dates:
• Nov 20: Preliminary Project Report
• Dec 13: Final Project Report Due

ECE U530 F’06 4

lect17.ppt

Preliminary Project Reports

• Due Monday, November 20
• Your report should include:
• A description of your project and what it does
• VHDL code -- should be commented
• Simulation results
• Plan for the rest of the semester
• Project Presentations:
• You should give a 5 minute presentation about your

project in class:

• What is your project
• What are the challenges
• What have you accomplished so far?

SLIDE 2

ECEU530

ECE U530 F’06 5

lect17.ppt

Calculator: Lab 5

ECE U530 F’06 6

lect17.ppt

Calculator Entity

library IEEE; use IEEE.std_logic_1164.all; entity Calc is port (sw: in STD_LOGIC_VECTOR(7 downto 0);

• - instruction and data input bus

reset: in STD_LOGIC; -- active high reset signal exc: in STD_LOGIC; -- execution signal, active high clk: in STD_LOGIC; -- clock signal dout: out STD_LOGIC_VECTOR (3 downto 0); -- data output cout: out STD_LOGIC -- 4th bit from tos,

• - indicates error flag

); end Calc;

ECE U530 F’06 7

lect17.ppt

Calculator Architecture

architecture Calc_arch of Calc is component ctrl port (reset: in STD_LOGIC; -- active high reset signal clk : in STD_LOGIC; -- clock signal exc : in STD_LOGIC; -- execution signal active high sw : in STD_LOGIC_VECTOR(7 downto 4); -- instruction sm : out STD_LOGIC; -- mux select signal sa : out std_logic_vector (2 downto 0); -- alu select ss : out std_logic_vector (1 downto 0)); -- stack select end component; component datapath port (reset : in STD_LOGIC; -- asynchronous reset din : in std_logic_vector (3 downto 0); -- input data dout: out std_logic_vector (3 downto 0); -- output data cout : out std_logic; -- carry, borrow or overlow flag sm : in std_logic; -- mux selector sa : in std_logic_vector (2 downto 0); -- alu select ss : in std_logic_vector (1 downto 0); -- stack select clk : in std_logic ); -- clock end component; begin

• - <<enter your statements here>>

end Calc_arch;

ECE U530 F’06 8

lect17.ppt

Controller Entity

library IEEE; use IEEE.std_logic_1164.all; entity ctrl is port ( reset: in STD_LOGIC; -- active high reset signal clk : in STD_LOGIC; -- clock signal exc : in STD_LOGIC; -- execution signal, active high sw : in STD_LOGIC_VECTOR (7 downto 4);

• - instruction input

sm: out STD_LOGIC; -- mux select signal sa: out std_logic_vector (2 downto 0); -- alu select ss: out std_logic_vector (1 downto 0) ); -- stack select ); end ctrl; architecture ctrl_arch of ctrl is begin

• - <<enter your statements here>>

end ctrl_arch;

SLIDE 3

ECEU530

ECE U530 F’06 9

lect17.ppt

Controller for Calculator

• Always go through all the states

Wait TOS1 TOS2 Reset EXE = 1

EXE = 0

PUSH

ECE U530 F’06 10

lect17.ppt

Controller for Calculator

• Push instruction
• TOS1: hold stack
• TOS2: hold stack, put input in temp register
• PUSH: push input
• Pop instruction
• TOS1: pop
• TOS2: hold stack
• TOS3: hold stack
• Add TOS1 + TOS2
• TOS1: Put TOS in temp register, pop stack
• TOS2: Add TOS to temp register, pop stack
• PUSH: Push result

ECE U530 F’06 11

lect17.ppt

Controller State Machine

• 3 processes:
• state register
• Next state function
• Output function

–What are the outputs –Are they Mealy or Moore? »Does it matter?

ECE U530 F’06 12

lect17.ppt

Memory Structures

• Register
• Register File
• ROM: Read only memory
• RAM: Random access memory
• Embedded RAM in FPGAs: Select RAM

SLIDE 4

ECEU530

ECE U530 F’06 13

lect17.ppt

Register (Eight-bit)

process(Clk) begin if rising_edge(Clk) then Q <= D; end if; end process; D (7 downto 0) Q(7 downto 0) Clk Clk Q(7) Q(6) Q(5) Q(1) Q(2) Q(3) Q(0) D(7) D(6) D(5) D(4) D(1) D(2) D(3) D(0) Q(4) This register has no reset

ECE U530 F’06 14

lect17.ppt

n-bit Register with Reset

entity EXAMPLE is generic (width : positive := 8); port ( DI : in STD_LOGIC_VECTOR ( width-1 downto 0); CLK : in STD_LOGIC; RST : in STD_LOGIC; DO : out STD_LOGIC_VECTOR (width-1 downto 0) ); end EXAMPLE; architecture ARCHI of EXAMPLE is begin process (CLK, RST) begin if RST = '1' then DO <= (others => ‘0’); elsif CLK'EVENT and CLK = '1' then DO <= DI ; end if; end process; end ARCHI;

ECE U530 F’06 15

lect17.ppt

Simplest Memory: Array stored in FFs

• The simplest memory is an array stored in flip-flops

ARCHITECTURE behavioral OF stack IS SUBTYPE four_bit IS std_logic_vector (3 downto 0); TYPE four_array IS ARRAY (3 downto 0) OF four_bit; SIGNAL stk, tmp : four_array; begin ... process (reset,clk) begin if reset = '1' then stk <= (OTHERS => "0000"); elsif clk'event and clk = '1' then stk <= tmp; end if; end process; end architecture;

ECE U530 F’06 16

lect17.ppt

Stack is an Array stored in FFs

• Declaration of STACK:

______ Flip-flops are inferred

• Different values can be stored in different locations of

the stack at different times

• Only top of stack is visible
• Difference between a stack and more general

memory: stack requires no address

SLIDE 5

ECEU530

ECE U530 F’06 17

lect17.ppt

Memories

• Organized as an indexed array of words.
• Value of the index for each word is the memory

address.

• Memory Operations
• read and write operations over some data element:

–bit, byte, word, etc.

• Random Access Memory (RAM):
• can address any location in memory and read data
• can address any location in memory and write data
• Read Only Memory (ROM):
• can address any location in memory and read data
• Data is preloaded into memory: no need to write it

ECE U530 F’06 18

lect17.ppt

RAMs and ROMs

• A ROM with n address input lines and m data output

lines contains 2^n entries, each m bits wide

• The ROM is said to have a height of 2^n and a width
• f m

A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 Address Data Inputs Outputs

ECE U530 F’06 19

lect17.ppt

Filling in a ROM

A B C O7 O6 O5 O4 O3 O2 O1 O0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

Address Contents

• ROM can be programmed to store arbitrary truth

tables

• Programming a ROM to implement a decoder
• peration:

ECE U530 F’06 20

lect17.ppt

Generic ROM (1)

LIBRARY ieee; USE ieee.std_logic_1164.all;

• ENTITY rom IS

GENERIC (bits: INTEGER:=8; -- # of bits per word words: INTEGER := 8); -- # of words in the memory PORT ( addr: IN INTEGER RANGE 0 to words-1; data: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) ); END rom;

SLIDE 6

ECEU530

ECE U530 F’06 21

lect17.ppt

Generic ROM (2)

ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := ("0000_0000", "0000_0010", "0000_0100", "0000_1000", "0001_0000", "0010_0000", "0100_0000", "1000_0000” ); BEGIN data <= memory(addr); END rom;

ECE U530 F’06 22

lect17.ppt

Generic ROM (3) – hexadecimal notation

ARCHITECTURE behavioral OF rom IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); CONSTANT memory: vector_array := (X"00", X"02", X"04", X"08", X"10", X"20", X"40", X"80” ); BEGIN data <= memory(addr); END rom;

ECE U530 F’06 23

lect17.ppt

Lab 2: A ROM is inferred

process (vec_in) begin case vec_in is when "0000" => vec_out <= "1111110" ; -- 0 when "0001" => vec_out <= "0110000" ; -- 1 when "0010" => vec_out <= "1101101" ; -- 2 when "0011" => vec_out <= "1111001" ; -- 3 when "0100" => vec_out <= "0110011" ; -- 4 when "0101" => vec_out <= "1011011" ; -- 5 when "0110" => vec_out <= "1011111" ; -- 6 when "0111" => vec_out <= "1110000" ; -- 7 when "1000" => vec_out <= "1111111" ; -- 8 when "1001" => vec_out <= "1110011" ; -- 9 when "1010" => vec_out <= "1110111" ; -- A when "1011" => vec_out <= "0011111" ; -- B when "1100" => vec_out <= "1001110" ; -- C when "1101" => vec_out <= "0111101" ; -- D when "1110" => vec_out <= "1001111" ; -- E when "1111" => vec_out <= "1000111" ; -- F when others => vec_out <= "-------" ; end case; end process;

ECE U530 F’06 24

lect17.ppt

Memory Block Diagram

• A basic memory system is shown

here:

• k address lines are decoded to

address 2k words of memory

• Each word is m bits
• Read and Write are single bit

control lines defining the simple memory operations m Data Input Lines k Address Lines Read Write m Data Output Lines Memory Unit 2k Words m Bits per Word k 1 1 m m

SLIDE 7

ECEU530

ECE U530 F’06 25

lect17.ppt

Memory Organization Example

• Example memory

contents:

• A memory with 3 address

bits & 8 data bits has:

• k = 3 and m = 8 so 23 = 8

addresses labeled 0 to 7.

• 23 = 8 words of 8-bit data

Memory Address Binary Decimal Memory Content

0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 0 2 1 0 1 1 0 0 0 1 0 1 1 3 0 0 0 0 0 0 0 0 1 0 0 4 1 0 1 1 1 0 0 1 1 0 1 5 1 0 0 0 0 1 1 0 1 1 0 6 0 0 1 1 0 0 1 1 1 1 1 7 1 1 0 0 1 1 0 0

ECE U530 F’06 26

lect17.ppt

Basic Memory Operations

• Read Memory Read a data value stored in memory:
• Place a valid address on the address lines
• Wait for the read data to become stable
• Write Memory Write a data value to memory:
• Place a valid address on the address lines and valid data on

the data lines

• Toggle the memory write control line
• Sometimes the read or write enable line is defined as a

clock with precise timing information (e.g. Read Clock, Write Strobe).

• Otherwise, it is just an interface signal
• Sometimes memory must acknowledge that it has completed

the operation -- handshaking

ECE U530 F’06 27

lect17.ppt

Memory Operation Timing

• Most basic memories are asynchronous
• Storage in latches or storage of electrical charge
• No clock
• Controlled by control inputs and address
• Timing of signal changes and data observation is critical to the operation
• Read timing:

Read cycle Clock Address Memory enable Read/ Write Data

• utput

20 ns T1 T2 T3 T4 T1 Address valid 65 ns Data valid

ECE U530 F’06 28

lect17.ppt

Memory Operation Timing

• Write timing:
• Critical times measured with respect to edges of write pulse (1-0-1):
• Address must be established at least a specified time before 1-0 and held for at

least a specified time after 0-1 to avoid disturbing stored contents of other addresses

• Data must be established at least a specified time before 0-1 and held for at least a

specified time after 0-1 to write correctly Write cycle Clock Address Memory enable Read/ Write Data input 20 ns T1 T2 T3 T4 T1 Address valid Data valid 75 ns

SLIDE 8

ECEU530

ECE U530 F’06 29

lect17.ppt

RAM Integrated Circuits

• Types of random access memory
• Static – information stored in latches
• Dynamic – information stored as electrical charges on capacitors

– Charge “leaks” off – Periodic refresh of charge required

• Dependence on Power Supply
• Volatile – loses stored information when power turned off
• Non-volatile – retains information when power turned off

ECE U530 F’06 30

lect17.ppt

Static RAM Cell

• Array of storage cells used to implement static RAM
• Storage Cell
• SR Latch
• Select input for

control

• Dual Rail Data

Inputs B and B

• Dual Rail Data

Outputs C and C

Select B RAM cell C C B S R Q Q

ECE U530 F’06 31

lect17.ppt

Static RAM Bit Slice

• Represents all circuitry that is required for 2n 1-bit words
• Multiple RAM cells
• Control Lines:

– Word select i – one for each word – READ/WRITE – Bit Select

• Data Lines:

– Data in – Data out

(a) Logic diagram Select S R Q Q B RAM cell C C B Select S R Q Q RAM cell X Word select Word select 2n 1 Data in Write logic Read/ Write Bit select S R Q Q X X X Word select Word select 1 Word select 2n Read/Write logic Data in Data out Read/ Write Bit select (b) Symbol RAM cell RAM cell RAM cell Data out Read logic 1

ECE U530 F’06 32

lect17.ppt

Read/

2n-Word × × × × 1-Bit RAM IC

• To build a RAM IC

from a RAM slice, we need:

• Decoder decodes

the n address lines to 2n word select lines

• A 3-state buffer
• on the data output

permits RAM ICs to be combined into a RAM with c × × × × 2n words

Word select Read/Write logic Data in Data out Write Bit select (b) Block diagram RAM cell RAM cell RAM cell Data input Chip select Read/Write Data

• utput

A3 A2 A1 A0 23 22 21 20 4-to-16 Decoder 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A3 A2 A1 A0 Data input Data

• utput

(a) Symbol Read/ Write Memory enable 16 x 1 RAM

SLIDE 9

ECEU530

ECE U530 F’06 33

lect17.ppt

RAM ICs with > 1 Bit/Word

• Word length can be quite high
• To better balance the number of words and word

length, use ICs with > 1 bit/word

• Example:
• 2 Data input bits
• 2 Data output bits
• Row select selects 4 rows
• Column select selects 2 pairs of columns

ECE U530 F’06 34

lect17.ppt

Cell Arrays and Column Selection

Data input Read/Write X X X A1 A0 RAM cell RAM cell 4 RAM cell 8 RAM cell 12 Read/Write logic Data in Data out Read/ Write Bit select RAM cell 1 RAM cell 5 RAM cell 9 RAM cell 13 Read/Write logic Data in Data out Read/ Write Bit select RAM cell 2 RAM cell 6 RAM cell 10 RAM cell 14 Read/Write logic Data in Data out Read/ Write Bit select RAM cell 3 RAM cell 7 RAM cell 11 RAM cell 15 Read/Write logic Data in Data out Read/ Write Bit select Column decoder 2-to-4 Decoder with enable 21 20 1 Column select 2 Enable 3 Chip select Data

• utput

Row select Row decoder A2 A3 X 2-to-4 Decoder 20 21 1 2 3

ECE U530 F’06 35

lect17.ppt

Tri-State Buffers

• The input signal is only connected to the output signal when the

enable signal is asserted

• Tri state buffers are used when multiple gates may need to drive

a single logical signal line

• Care must be taken to ensure that only one output is enabled to

drive the output signal at any given time

ENABLE IN OUT

1 1 1 1 Z Z 1 Out E In

ECE U530 F’06 36

lect17.ppt

Using tri-state buffers

E0 I0 E1 I1 E2 I2 OUT

Tri-state buffers are like a distributed mux 1 1 1 1 Z Z 1 Out E In

SLIDE 10

ECEU530

ECE U530 F’06 37

lect17.ppt

Registers Connected by a Tri-state Bus

• Can make any register transfer R[i]←

← ← ←R[j]

• Can’t have Gi = Gj = 1 for ij
• Violating this constraint gives low resistance path from

power supply to ground

ECE U530 F’06 38

lect17.ppt

Generic RAM (1)

LIBRARY ieee; USE ieee.std_logic_1164.all;

• ENTITY ram IS

GENERIC (bits: INTEGER := 8; -- # of bits per word words: INTEGER := 16); -- # of words in the memory PORT ( wr_ena, clk: IN STD_LOGIC; addr: IN INTEGER RANGE 0 to words – 1; data_in: IN STD_LOGIC_VECTOR(bits – 1 downto 0); data_out: OUT STD_LOGIC_VECTOR(bits – 1 downto 0) ); END ram;

ECE U530 F’06 39

lect17.ppt

Generic RAM (2)

ARCHITECTURE behavioral OF ram IS TYPE vector_array IS ARRAY (0 TO words-1) OF STD_LOGIC_VECTOR(bits – 1 DOWNTO 0); SIGNAL memory: vector_array; BEGIN PROCESS(clk, wr_ena) BEGIN IF(wr_ena=‘1’) THEN IF (clk’EVENT AND clk=‘1’) THEN memory(addr) <= data_in; END_IF; END IF; END PROCESS; data_out <= memory(addr); END ram;

ECE U530 F’06 40

lect17.ppt

Microprocessor Register File

• For read operations,

functionally the regfile is equivalent to a 2-D array of flip-flops with tristate outputs

• n each
• MUX, but distributed
• Unary control
• Cell with added write logic:

These circuits are just functional abstractions of the actual circuits used.

SLIDE 11

ECEU530

ECE U530 F’06 41

lect17.ppt

Multi-ported Memory

• Motivation:
• Consider CPU core register file:

– 1 read or write per cycle limits processor performance. – Complicates pipelining. Difficult for different instructions to simultaneously read or write regfile. – Common arrangement in pipelined CPUs is 2 read ports and 1 write port – 2 read ports: dual ported memory sela selb selc dataa datab datac Regfile

ECE U530 F’06 42

lect17.ppt

Dual-ported Memory Internals

• Add decoder, another set of

read/write logic, bits lines, word lines:

• Example cell: SRAM
• Repeat everything but cross-

coupled inverters.

• This scheme extends up to a

couple more ports, then need to add additional transistors.

deca decb

cell array

r/w logic r/w logic

data ports address ports b2 b2 b1 b1

WL2 WL1

ECE U530 F’06 43

lect17.ppt

Behavioral Description of a Register File

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity regfile is port(write_data: in std_logic_vector(31 downto 0); dst_addr,src1_addr,src2_addr: in UNSIGNED(4 downto 0); write_cntrl: in std_logic; src1_data,src2_data: out std_logic_vector(31 downto 0)); end regfile;

Register File src1_addr src2_addr dst_addr write_data 32 bits src1_data src2_data 32 words write_cntrl

ECE U530 F’06 44

lect17.ppt

Behavioral Description of a Register File, asynchronous

architecture process_behavior of regfile is type reg_array is array(0 to 31) of std_logic_vector (31 downto 0); begin regfile_process: process(src1_addr,src2_addr,dst_addr,write_cntrl) variable data_array: reg_array := ( (X”00000000”), (X”00000000”), . . . (X”00000000”)); variable addrofsrc1, addrofsrc2, addrofdst: integer; begin addrofsrc1 := conv_integer(src1_addr); addrofsrc2 := conv_integer(src2_addr); addrofdst := conv_integer(dst_addr); if write_cntrl = ‘1’ then data_array(addrofdst) := write_data; end if; src1_data <= data_array(addrofsrc1) after 10 ns; src2_data <= data_array(addrofsrc2) after 10 ns; end process regfile_process; end process_behavior;

SLIDE 12

ECEU530

ECE U530 F’06 45

lect17.ppt

Xilinx FPGA Architecture

• CLB

Configurable Logic Block IOB Input/Output Block PSM Programmable Switch Matrix PIP Programmable Interconnect Point

ECE U530 F’06 46

lect17.ppt

Using SRAM to Implement Logic

ECE U530 F’06 47

lect17.ppt

A Simplified Logic Slice

ECE U530 F’06 48

lect17.ppt

Mapping a Function to a 4-input LUT

SLIDE 13

ECEU530

ECE U530 F’06 49

lect17.ppt

CLB Used as RAM

ECE U530 F’06 50

lect17.ppt

Memory Blocks in FPGAs

• LUTs can double as small RAM blocks:
• 4-LUT is really a 16x1 memory. Normally

we think of the contents being written from the configuration bit stream, but Virtex architecture (and others) allow bits of LUT to be written and read from the general interconnect structure.

• achieves 16x density advantage over using

CLB flip-flops.

• Furthermore, the two LUTs within a slice

can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16x1-bit dual-port synchronous RAM.

• The Virtex-E LUT can also provide a 16-bit

shift register of adjustable length.

• Newer FPGA families include larger on-

chip RAM blocks (usually dual ported):

• Called block selectRAMs in Xilinx Virtex

series

• 4k bits each

ECE U530 F’06 51

lect17.ppt

RAM16X1S

O D WE WCLK A0 A1 A2 A3

RAM32X1S

O D WE WCLK A0 A1 A2 A3 A4

RAM16X2S

O1 D0 WE WCLK A0 A1 A2 A3 D1 O0

= =

LUT LUT

• r

LUT

RAM16X1D

SPO D WE WCLK A0 A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3

• r

Distributed RAM

• CLB LUT configurable as Distributed

RAM

• A LUT equals 16x1 RAM
• Implements Single and Dual-Ports
• Cascade LUTs to increase RAM size
• Synchronous write
• Synchronous/Asynchronous read
• Accompanying flip-flops used for

synchronous read

ECE U530 F’06 52

lect17.ppt

DSP Coefficients Small FIFOs Scratch Pad

16x1

Distributed RAM

• Single-port
• Dual port
• Cascadable

Cache Tag memory Large FIFOs Packet buffers Video line buffers

Block RAMs

• 4Kbit blocks
• True dual-port

SDRAM SGRAM PB SRAM DDR SRAM ZBT SRAM QDR SRAM

High-Performance External Memory Interfaces

• DDR I/O
• SSTL, HSTL, CTT

Spartan-IIE Memory Hierarchy

D CL K A3 A2 A1 A0 Q

SRL16

D CL K A3 A2 A1 A0 Q

SRL16E

C E

Shift Register LUT

• 16 registers, 1 LUT
• Compact & fast

Pipelining Buffers

Block RAM

4Kx1 2Kx2 1Kx4 512x8 256x16

Port A Port B

Collaboration with memory vendors IDT, Cypress, Micron, NEC, Samsung, Toshiba...

Bytes Kilobytes Megabytes

SLIDE 14

ECEU530

ECE U530 F’06 53

lect17.ppt

FPGA Embedded Memory Summary

• Fast distributed RAM
• Data right beside logic
• Memory requirements solved by Block RAM
• Single and True Dual-Port RAM implementations
• FIFO for buffering data
• Data width conversion
• Cache
• Register stacks
• CAM for high-speed parallel searches
• Many more
• Direct connection to external high-speed memory

ECE U530 F’06 54

lect17.ppt

Memories in VHDL for Xilinx

• Look at the Language Templates in Project Manager

for how to describe memories in VHDL for FPGAs

• Synthesis Templates:
• Distributed RAM
• Block RAM
• Component Instantiations